Abstract: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

Abstract: A nonvolatile memory cell includes a gate controlled diode steering element and a resistivity switching element.

Abstract: A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.

Abstract: A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.

Abstract: A hybrid topography mask is designed for facilitating the fabrication of a semiconductor wafer. The hybrid mask includes a substrate having a light receiving surface. The light receiving surface defines a plane. Pluralities of pattern elements are etched into and out of the light receiving surface. Each of the plurality of pattern elements defines a pattern surface that is parallel to the light receiving surface. Pattern sides extend between the pattern elements and the light receiving surface. Each of the pattern sides extends perpendicularly between the light receiving surface and the pattern elements. The hybrid mask also includes a tapered sub-resolution assist element etched out of the light receiving surface to position the mask with respect to the semiconductor wafer. The tapered sub-resolution assist element is fabricated to avoid affecting any photoresist residue from the sub-resolution assist element's presence on the semiconductor wafer disposed adjacent the hybrid mask.

Abstract: The surface of a conductive layer such as a conductive nitride, a conductive silicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.

Abstract: A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant conce

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Abstract: A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.

Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Abstract: A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode.

Abstract: A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, and etching the underlying layer using both the first and the second photoresist patterns as a mask.

Abstract: Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a carbon layer (“carbon liner”) above the CNT layer, wherein the carbon liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.

Abstract: Methods in accordance with this invention form microelectronic structures, such as non-volatile memories, that include carbon layers, such as carbon nanotube (“CNT”) films, in a way that protects the CNT film against damage and short-circuiting. Microelectronic structures, such as non-volatile memories, in accordance with this invention are formed in accordance with such techniques.

Abstract: Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a boron nitride layer (“BN liner”) above the CNT layer, wherein the BN liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.