Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure, for reversibly modifying nanostructures, and for manipulating the electronic properties of nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures. Ligands of the present invention are also useful for manipulating the electronic properties of nanostructure compositions (e.g., by modulating energy levels, creating internal bias fields, reducing charge transfer or leakage, etc.).

Abstract: In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.

Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure, for reversibly modifying nanostructures, and for manipulating the electronic properties of nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures. Ligands of the present invention are also useful for manipulating the electronic properties of nanostructure compositions (e.g., by modulating energy levels, creating internal bias fields, reducing charge transfer or leakage, etc.).

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Abstract: A data storage device includes one or more data paths through electrical contacts of the data storage device. The data paths are operably connected to allow bits to be transferred into and out of the data storage device. The data storage device stores an indication of a number of the one or more data paths in a configuration register. A method includes performing, while the data storage device is operatively coupled to a host device, receiving a command of the host device to read the configuration register and providing the indication via at least one of the one or more data paths. Providing the indication enables indicating to the host device the number of the one or more data paths.

Abstract: Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can take into account the target programmed state of one or more adjacent memory cell. The amount of programming is verified after each programming pulse and the standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states. The verify level is preferably virtually offset by biasing adjacent word lines instead of actually offsetting the standard verify level. For soft-programming erased cells, neighboring cells on both adjacent word lines are taken into account.

Abstract: A data storage device includes one or more electrical contacts and one or more data paths through the electrical contacts. The one or more electrical contacts enable bits to be transferred into and out of the data storage device via the one or more data paths. The data storage device also includes a memory that stores an indication of a number of the one or more data paths. The data storage device is configured to provide the indication via at least one of the one or more data paths while the data storage device is operatively coupled to a host device to indicate to the host device the number of the one or more data paths.

Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.

Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract: A photolithography mask including a plurality of mask features. Adjacent mask features are separated by a gap and are offset from each other such that individual mask features have one-side dense portions and two-side dense portions. Also a photolithography method that includes a step of providing a substantially opaque mask having N stepped rows of offset, substantially transparent, rectangular mask features, where N is an integer and N?2. The method also includes illuminating a photoresist layer located over an underlying material with dipole illumination through the substantially transparent, rectangular mask features in the substantially opaque mask to form 2N rows of exposed regions in the photoresist layer. The exposed regions have a substantially elliptical or substantially circular shape when viewed from above the photoresist layer.

Abstract: Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.

Abstract: A method in a data storage device receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a second sub-block of data. The method also includes initiating an ECC operation to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data block, first additional ECC data that is external to the data block is retrieved and a second ECC operation is initiated to process the first sub-block of data using the first additional ECC data.