Abstract: When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the volatile memory to values above a verify voltage. While those threshold voltages remain substantially at those levels, the device raises the threshold voltages of other cells of the volatile memory to values below the verify voltage. In the end, every cell stores one or more bits from each plurality of bits. Preferably, all the cells share a common wordline. A data storage device operates similarly with respect to storing pluralities of bits generated by an application running on the system.

Abstract: Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M?1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Abstract: The present invention discloses methods for improving data-retrieval times from a non-volatile storage device. A method for preloading data to improve data-retrieval times from a non-volatile storage device, the method including the steps of: providing a cache memory for preloading the data upon a host-system request to read the data; determining that a plurality of data segments that constitute a non-contiguous data object, stored in the storage device such that at least one data segment is non-contiguous to a preceding data segment in the data object, are in a predictable sequence; and preloading a non-contiguous next data segment in the predictable sequence into the cache memory after loading a current data segment into a host system from the cache memory, wherein the next data segment is preloaded prior to the host-system request to read the next data segment.

Abstract: Systems and methods of overlapping error correction operations are disclosed. A method at an encoder device includes receiving data bits to be encoded including a first bit, a second bit, and a third bit. A first encode operation to encode a first group of the data bits is initiated to generate a first codeword. The first group of the data bits includes the first bit and the second bit, but not the third bit. A second encode operation to encode a second group of the data bits is initiated to generate a second codeword. The second group of the data bits includes the second bit and the third bit, but not the first bit.

Abstract: A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L<M, by comparing the gain-adjusted threshold voltage values to read threshold voltage levels of a fresh memory device. In another approach, the read threshold voltage levels of the fresh device are gain adjusted for reading non-gain-adjusted threshold voltage values from the cells which have experienced data retention loss.

Abstract: A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

Abstract: A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.

Abstract: Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

Abstract: An improved memory card includes an interface for receiving content from an appliance, a primary memory, a secondary memory, and primary controller. The primary controller is configured to selectively write the content only on the primary memory card, or only on the secondary memory card, or on both memories. The improved memory card also includes an enclosure for enclosing the primary memory, the secondary memory, the primary host interface and the primary controller. The improved memory card also includes a user interface that includes a user-operable mode switch that is switchable between a “full capacity” mode and a “full redundancy” mode. In the “full capacity” mode the secondary memory is used for recording genuine content, whereas in the “full redundancy” mode the secondary memory is used for backing up content that has been recorded on the primary memory. A digital shoebox is also provided, which can use improved memory cards and conventional memory cards alike for archiving content.

Abstract: The present invention discloses methods for delivering code to a host system including the steps of: accepting a CPU request, from a host-system processor of the host system, for a code segment; initiating a retrieval process to retrieve the code segment; upon expiration of a predetermined time, checking whether the code segment is ready for delivery; upon the predetermined time expiring before the code segment is ready for delivery, providing an SWI that is different than the code segment; and upon the predetermined time expiring after the code segment is ready for delivery, providing the code segment. Preferably, the SWI causes the host-system processor to jump to a reset-vector address. Most preferably, the reset-vector code, located at the reset-vector address, includes a command to request the code segment again.

Abstract: A condition of a subject is monitored by a wearable recording unit that adaptively records various signals associated with the condition of the subject. The various signals are recorded by the wearable recording unit using a recording plan that is contextually adaptively updated to the monitored subject from one recording session to another based on the result of the analysis of previous recording sessions.

Abstract: A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and a second value stored at a second memory element of the plurality of memory elements. The controller is configured to test whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the first memory element. The controller is configured to provide a data value corresponding to the first memory element, where the data value is determined at least in part based on a result of the test.

Abstract: Data storage devices and methods to combine user content with supplemental content at a data storage device are disclosed. The data storage device includes a host interface, a controller coupled to the host interface, a first storage area coupled to the controller, and a second storage area coupled to the controller. The host interface is configured to enable the data storage device to receive one or more user content items from a host device when the data storage device is operationally coupled to the host device. The controller is configured to store the one or more user content items in the first storage area. The controller is also configured to combine a particular supplemental content item stored in the second storage area with a particular user content item from among the one or more user content items.

Abstract: A storage system for exchanging data with a host system, the storage system including a plurality of storage devices, each of the storage devices including: a non-volatile memory, wherein a fixed static-IP address resides in the non-volatile memory, the fixed static-IP address being common to two or more of the plurality of storage devices, and the fixed static-IP address providing enablement of a storage-device functionality of the storage device; a physical interface for operationally connecting the storage device with the host system; and a memory controller for: controlling the respective non-volatile memory; and exchanging data, using a communication protocol, via the respective fixed static-IP address. For at least one of the storage devices, the respective fixed static-IP address may be pre-loaded into the respective non-volatile memory during manufacture, or installed in the respective non-volatile memory after manufacture.

Abstract: Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device.

Abstract: A flash memory is managed by reserving one or more cells as flag cells to represent the number N of bits to store in the cells of a memory block, selecting the value of N from at least three candidates, and programming the flag cell(s) to represent the selected value. A flash memory is managed by selecting a value of the number N>2 of bits to store in the cells of a portion (e.g. a block or page) of the memory, reserving one other cell of the memory as a flag cell to represent how many bits actually are stored in each cell of the portion, and, as the cells of the portion are successively programmed with 1?n?N bits, programming the flag cell to represent n.

Abstract: A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system.

Abstract: A removable storage device with a processor and a non-volatile memory, and a method for using a removable storage device, are provided to emulate the computer system. The storage device stores in the non-volatile memory data it obtained from a first computer system, the data containing computer applications. When the storage device is removably connected to a second computer system and the second computer system is associated with a computer peripheral device, the processor in the storage device is instructed to emulate the original process environment of the first computer system.

Abstract: A card adapter includes a first memory card interface configured to be connected to a first memory card. The first memory card is associated with a first file system. The card adapter includes a second memory card interface that is configured to be connected to a second memory card. The second memory card is associated with a second file system. The card adapter also includes a host interface configured to connect to a host. The card adapter includes a controller operatively interposed between the first and second memory card interfaces and the host interface. The controller is configured to control the first memory card interface and the second memory card interface to control connections between each memory card that is connected thereto with the host. The controller is also configured to operate in each of two selectable modes. In a first mode the controller is operative to emulate a virtual file system that presents to the host the first file system and the second file system as a unified image.

Abstract: A flash memory that supports N>1-bit programming is managed by, for at least one block of the memory, selecting the value of N to use for the block, designating one or more cells of the block as flag cells, and programming the flag cells to represent the selected value of N. Preferably, N is encoded according to whether the threshold voltages of the flag cells are greater or less than a reference voltage common to all values of N. The other cells of the block then are programmed in accordance with the selected value of N. N and its flag cells are selected when the block is first used to store data. Subsequent to an erasure of the block, a different value of N may be selected.