Abstract: A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.

Abstract: A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

Abstract: To store N bits of M?2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

Abstract: A device for integrating file systems includes a plurality of storage device interfaces. Each storage device interface is operatively coupleable to a corresponding storage device, and each storage device has a corresponding storage device file system. The device also includes a host interface and a hub configured for operatively connecting between the storage device interfaces and the host interface. The hub is operative to create a virtual file system that aggregates the storage device file systems. The virtual file system is configured to represent to a host, via the host interface, each file of a first group and to refrain from representing to the host each file of a second group, where the files are stored in one or more of the plurality of storage devices. Each file of the first group satisfies a first condition and each file of the second group fails to satisfy the first condition.

Abstract: Programmer's data that is transferred from a programming device (160) to a storage device (100) is initially stored in a memory device (120) of the storage device (100) by using a durable data-retention storage setup (210). After the storage device is embedded in a host device (170), the programmer's data is internally (i.e., in the storage device) read from the memory device and rewritten into the memory device by using a conventional storage setup (220). Using a durable data-retention storage setup may include temporarily (i.e., before the storage device is embedded in a host) operating selected memory cells (124) of the memory device as conventional single-bit per cell (SBC) cells or as unconventional multi-bit per cell (MBC) cells. After the storage device (100) is embedded in a host device (170), the programmer's data, or selected parts thereof, is read from the memory device (120) and rewritten into it by operating selected memory cells (126, 128) of the memory device as conventional MBC cells.

Abstract: A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller.

Abstract: A host device includes an electrical activity monitoring (EAM) module that is configured to monitor the electrical activity of a slave storage device interfaced with the host device. Responsive to the value of, or change in, the electric current fed to the slave storage device being at or near a certain level, or within a predetermined range, the EAM module notifies the host device that the slave storage device has pending service request(s) or information for the host device.

Abstract: Systems and methods for reading data are disclosed. In a particular embodiment, a method includes measuring characteristics of a plurality of cells at a memory. The characteristics correspond to a plurality of values including a first value stored at a particular cell and a second value stored at a second cell of the memory. The method includes testing whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the particular cell, and providing a data value corresponding to the particular cell. The data value is determined at least in part based on a result of the testing.

Abstract: Apparatus, methods and computer-code are disclosed where an impending decoupling between a peripheral device and a host is detected. In some embodiments, in response to the detected impending disconnection, a user alert signal is generated. In some embodiments, an ‘onboard detector’ that is associated with housing of the peripheral device and operative to detect the impending disconnection is provided. In some embodiments, the user alert signal is generated in accordance with inter-device data flow between the host and the peripheral device. Exemplary peripheral devices include but are not limited to transient storage devices such as a USB flash drives (UFD).

Abstract: A system for enforcing a storage allocation usage right(s) for an application may include a controllable storage and a storage manager to control the access of the application to the storage according to an associated storage allocation usage right. A SIM card for enforcing a storage allocation usage right for an application may include an application register to store an access rule of the storage allocation usage right(s) and an APREC module to identify the application and thereby an access rule to enable controlling of the access of the application to storage according to the storage allocation usage right. A high-capacity SIM card for enforcing a storage allocation usage right for an application may include a storage; a storage manager to control the access of an application to the storage according to an associated access rule of the storage allocation usage right; and an APREC module.

Abstract: A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an array of memory cells, wherein the memory cell is adjacent to and in electrical field communication with the addressed memory cell. A threshold voltage of the addressed memory cell is measured at each of the at least two different applied voltage levels. At least two of the measured threshold voltages of the addressed memory cell are converted to one or more bit values stored in the addressed memory cell. The bit values are provided to a host of the memory system. An apparatus implementing the method is also disclosed.

Abstract: A method in a data storage device for storing a plurality of data bits into a non-volatile memory includes transforming a plurality of data bits to be stored in a non-volatile memory device to generate a plurality of transformed data bits. The method further includes generating a parity bit corresponding to the plurality of transformed data bits, transforming the parity bit, and storing the plurality of data bits and the transformed parity bit in the non-volatile memory device. Each of the plurality of data bits and the parity bit form an all-one codeword.

Abstract: A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.

Abstract: A file replacement system includes a storage device, a host, and a server. In a file replacement transaction one or more files that are stored in the storage device are replaced in the storage device by one or more files that are provided by the server. The storage device monitors access to the files stored therein and updates an access tracking table with segment access information that pertains to access to segments of the files. While the file replacement transaction is in progress, the storage device delivers the segment access information to the server, and, based on the segment access information and file replacement criteria, the server determines a credit to which the end-user is entitled for the replaced files. The server calculates an outstanding balance for the file replacement transaction from the credit owing to the end-user for the replaced files and from the cost of the replacement files.

Abstract: In one aspect, a system for indexing transactions over a plurality of communication lines is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with one another. Each of the storage devices is configured to store data. The communication lines facilitate communications between the host controller and the plurality of storage devices. A selected one of the storage devices is configured to function as a transaction indexer to monitor the communication lines and index and store selected transaction information associated with operations that occur over the communication lines. While the host controller may be arranged to configure the transaction indexer, the transaction monitoring, indexing and storing are performed substantially automatically by the transaction indexer without requiring further instructions from the host controller.

Abstract: A method for storing data includes providing a memory package including an integrated circuit containing a non-volatile memory and counter circuitry. The data is written to the non-volatile memory. The counter circuitry is operated to maintain a count of write operations performed on the non-volatile memory. The data and the count from the memory package are received at a controller, separate from the memory package, and the data is authenticated in response to the count.

Abstract: A storage device having prioritized-erasure capabilities including: a memory for storing data, the memory having at least one flash unit, wherein each flash unit has a plurality of blocks; and a controller configured: to write the data into the plurality of blocks; to assign an erasure-priority to each block, wherein the erasure-priority correlates with an erasure-priority of the data; and to erase the data in each block according to the erasure-priority of each block upon receiving an emergency-erase command. Preferably, the controller is configured to perform the writing of the data into the plurality of blocks in an arbitrary order in a first flash unit, and the writing into subsequent flash units is performed in correlation with the order in the first flash unit. Preferably, the erasing includes aborting erasure, before completing the erasure, for at least some of the plurality of blocks.

Abstract: Different peripheral devices of the present invention include: a display panel interface to which is reversibly operationally attachable a display panel and a power interface for receiving power from a host; a display panel to which are individually reversibly operationally attachable display panels for displaying respective aspects of the device's operation; a display panel for providing a semantic display of the device's mode of operation and a power interface for receiving power from a host; or a display panel, a controller for operating the display panel in accordance with ambient conditions, and a power interface for receiving power from a host. A system includes an appliance, an ornament dock and a peripheral device, reversibly operationally attachable to either the appliance or the ornament dock, that operates a display panel in accordance with data received from the appliance.

Abstract: An apparatus, method and computer readable medium for disambiguating commands with respect to logical protocols is disclosed herein. In some embodiments, commands are disambiguated in accordance with an extent of device usage since a most recent device reset event. In some embodiments, commands are disambiguated in accordance with one or more command target parameters of a current command and/or one or more previous commands. In some embodiments, commands are disambiguated in accordance with a security policy and/or a data access policy and/or an indication of a data damage risk.

Abstract: A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method.