Abstract: A system and method is disclosed for providing zero data in response to a host data read directed to a logical address that is not associated with valid data. The system may be a non-volatile memory system including non-volatile memory and a controller configured to determine whether a logical address in a read command is associated with valid data. The controller may be configured to generate, store in non-volatile memory and retrieve from that non-volatile memory a zero data entry. The controller may also be configured to include any associated encryption key or logical address in the generation of the zero data in order to satisfy data path protection and/or encryption requirements for the non-volatile memory system. Storage and retrieval of the zero data may be via the non-volatile memory array or only the data latches of the non-volatile memory.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.

Abstract: Apparatus and method for determining when to save values of read counters are disclosed. Read counters store values that indicate the number of reads in respective blocks of a memory device. The values of the read counters may be stored in volatile memory, and may be periodically stored to non-volatile memory. The frequency at which the values of the read counters are stored to non-volatile memory may be dependent on the read disturb effect. One measure of the read disturb effect may be based on the characteristics of the respective blocks of the memory device, such as whether the respective block is open/closed, has on-chip copy, and whether the read is to a boundary wordline.

Abstract: A non-volatile memory system may include a controller that issues data transfer commands to have data units associated with a host read request transferred from non-volatile memory to a temporary storage area before the data is sent to a host. The controller may be configured to generate a schedule that identifies when the data transfer commands are issued. The schedule may be generated according to one of a plurality of scheduling schemes, each with a different priority in having the data units transferred to the temporary storage area. Which scheduling scheme the controller selects may depend on a queue depth of a read request queue.

Abstract: A storage device and method for detecting and handling burst operations are provided. In one embodiment, a method for operating a storage device in burst mode is provided. The storage device senses a change in behavior of a host in communication with the storage device, determines whether the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode by comparing the sensed change in behavior with prior changes in behavior that triggered prior burst modes in the storage device, and in response to determining that the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode, operates the storage device in burst mode. Other embodiments are provided.

Abstract: A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in optimizing a compaction process. The compaction process may include segregating into separate compaction destination blocks valid data based on the stored validity status such that data valid in both the host file system directory and the logical-to-physical mapping table is in compaction destination blocks separate from data having valid logical-to-physical mapping entries but associated with deleted host file system directory entries.

Abstract: A memory system and method are provided for performing garbage collection on blocks based on their obsolescence patterns. In one embodiment, a controller of a memory system classifies each of the plurality of blocks based on its obsolescence pattern and performs garbage collection only on blocks classified with similar obsolescence patterns. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A memory system and method for reducing peak current consumption. In one embodiment, a method is provided that is performed in a memory system comprising a memory with a plurality of blocks, wherein each block has a peak current consumption. In this method, a plurality of metablocks is created, wherein each metablock is created by grouping together blocks with complementary peak current consumption. Next, the metablocks are programmed. Because each of the metablocks has blocks with complementary peak current consumption, each of the metablocks has similar peak current consumption when programmed. Other embodiments are provided.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

Abstract: A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged, which may reduce the impact that the noise has on the frequency of the ring oscillator output signal. In some embodiments, a regulator may supply a regulated voltage to the ring oscillator. The regulator may reduce the impact of the noise for low frequency components of the noise, while the frequency divider may reduce the impact for high frequency of the noise.

Abstract: A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

Abstract: A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify further data sets that a host is likely to request.

Abstract: A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Abstract: The apparatus to transfer heat from memory components includes a first non-volatile memory component and a second non-volatile memory component. The apparatus includes a heat spreading material in thermal communication with the first non-volatile memory component and the second non-volatile memory component. The heat spreading material is configured to transfer heat from the first non-volatile memory component and the second non-volatile memory component.

Abstract: A memory system and method for power management are disclosed. In one embodiment, a memory system maintains a variable credit value indicating an amount of power currently available for memory operations in the memory system, the variable credit value having an upper limit that reflects a maximum power limit for the memory system. The memory system receives a command to perform a memory operation, wherein a plurality of resources are required to perform the memory operation, each resource being associated with a credit value. Prior to performing the memory operation, the memory system checks whether the variable credit value indicates that there is sufficient power available to perform the memory operation. Resource(s) required to perform the memory operation that are already being used in the memory system are not counted against the variable credit value.

Abstract: A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.

Abstract: A ring with a biometric sensor is provided. In one embodiment, the ring comprises a ring body, a biometric sensor positioned in the ring body and configured to sense a biometric feature, a memory configured to store a biometric feature of an authorized user, and a controller. The controller is configured to determine whether the biometric feature sensed by the biometric sensor matches the biometric feature stored in the memory, and in response to determining that the biometric feature sensed by the biometric sensor matches the biometric feature stored in the memory, enable a function of the ring.

Abstract: Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a non-volatile memory system compares a metric reflecting wear of a memory block to a wear leveling window and determines whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block. The memory management module performs a wear leveling operation on the memory block in response to determining that the metric reflecting wear of the memory block falls outside the wear leveling window and determining that the wear leveling indicator does not restrict performing a wear leveling operation on the memory block. After performing the wear leveling operation, the memory management module places the memory block on a free block list.