Patents Assigned to SanDisk Technologies Inc.
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Patent number: 9361986Abstract: A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.Type: GrantFiled: September 18, 2012Date of Patent: June 7, 2016Assignee: SanDisk Technologies Inc.Inventors: Jian Chen, Sergei Gorobets, Steven Sprouse, Tien-Chien Kuo, Yan Li, Seungpil Lee, Alex Mak, Deepanshu Dutta, Masaaki Higashitani
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Patent number: 9362338Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.Type: GrantFiled: March 3, 2014Date of Patent: June 7, 2016Assignee: SanDisk Technologies Inc.Inventors: Naoki Takeguchi, Hiroaki Iuchi
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Patent number: 9361991Abstract: A method of searching for a boundary between a written portion and an unwritten portion of an open block may include performing a word line by word line binary search of a first physical area of the open block to identify a last written word line of the first physical area of the block, and subsequently, searching in at least a second physical area of the open block based on the last written word line of the first physical area of the block as identified by the binary search.Type: GrantFiled: December 23, 2014Date of Patent: June 7, 2016Assignee: SanDisk Technologies Inc.Inventors: Yew Yin Ng, Gautam Dusija, Dennis S. Ea, Mrinal Kochar
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Patent number: 9354824Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: GrantFiled: January 8, 2016Date of Patent: May 31, 2016Assignee: SanDisk Technologies, Inc.Inventor: William Kwei-Cheung Lam
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Patent number: 9355713Abstract: In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.Type: GrantFiled: October 30, 2014Date of Patent: May 31, 2016Assignee: SanDISK Technologies Inc.Inventors: Jianmin Huang, Bo Lei, Jun Wan, Gerrit Jan Hemink, Steven T. Sprouse, Dana Lee
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Patent number: 9355735Abstract: Techniques for detecting word line layers which are shorted together due to a defect in a three-dimensional stack memory device, and for recovering data. The memory device comprises blocks of memory cells in which each block has a separate stack of word line layers but the word line layers at a common height in the different stacks are connected. A process to detect a short circuit occurs when an nth word line layer (WLn) in an ith block fails to successfully complete programming. A determination is made as to whether WLn is shorted to WLn?1 and/or WLn+1. If WLn is shorted to WLn+1 but not WLn?1 in the ith block, a recovery read process is performed to read the data which has been programmed into the memory cells of WLn of the previously-programmed blocks. The recovery read process uses upshifted control gate read voltages due to the short circuit.Type: GrantFiled: February 20, 2015Date of Patent: May 31, 2016Assignee: SanDisk Technologies Inc.Inventors: Jian Chen, Jiahui Yuan, Yingda Dong, Charles Kwong
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Patent number: 9356074Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: GrantFiled: November 17, 2014Date of Patent: May 31, 2016Assignee: SanDisk Technologies Inc.Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Patent number: 9355022Abstract: Systems and method for performing intelligent flash management are disclosed. A controller may determine if a write pattern exists between a set of writes associated with a first data chunk and a set of writes associated with a second data chunk based on whether a number of writes for first data chunk is equal to a number of writes for second data chunk; a degree to which a sequence of logical block address for the first data chunk matches the sequence of logical block addresses for the second data chunk; and a degree to which a size of each write for the first data chunk matches a size of each write for the second data chunk. The controller may then perform storage management operations based on whether or not a write pattern exists.Type: GrantFiled: March 4, 2013Date of Patent: May 31, 2016Assignee: SanDisk Technologies Inc.Inventors: Narendhiran Chinnaanangur Ravimohan, Vithya Kannappan, Saranya Nedunchezhiyan
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Patent number: 9349468Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.Type: GrantFiled: August 25, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies, Inc.Inventors: Kenneth Louie, Khanh Nguyen, Hao Nguyen
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Patent number: 9349740Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.Type: GrantFiled: January 24, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Donovan Lee, Vinod R Purayath, James Kai
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Patent number: 9349458Abstract: Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.Type: GrantFiled: October 16, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Kenneth Se Mon Louie, Khanh Nguyen
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Patent number: 9349478Abstract: A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. A programming operation avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn?1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn?1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.Type: GrantFiled: September 29, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Jiahui Yuan, Yingda Dong, Charles Kwong, Hong-Yan Chen, Liang Pang
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Patent number: 9349452Abstract: A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.Type: GrantFiled: March 7, 2013Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Mohan V. Dunga, Masaaki Higashitani
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Patent number: 9349479Abstract: One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block.Type: GrantFiled: November 18, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Rohit Sehgal, Niles Yang, Abhilash Kashyap
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Patent number: 9349476Abstract: Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify are disclosed. According to one aspect, a method for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify includes performing a program verify operation after a write to a non-volatile memory, where the program verify mechanism reports a pass or fail based on an existing measurement threshold value, and dynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations.Type: GrantFiled: February 21, 2013Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventor: Assaf Pe'er
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Patent number: 9343171Abstract: An erase operation for a memory cells in a block provides a consistent and sufficient erase depth regardless of the number of programmed word lines in the block. A lower erase-verify voltage is used for a first-programmed word line of a set of word lines than for remaining word lines in the set. As a result, the resistance of a memory cell of the first-programmed word line dominates during sensing of the NAND string so that the number of erase loops can be controlled in a predictable way regardless of the number of programmed word lines. The lower erase-verify voltage can be optimized so that it does not change the number of erase loops to complete an erase operation, compared to the case where a common erase-verify voltage is used on all word lines.Type: GrantFiled: February 9, 2015Date of Patent: May 17, 2016Assignee: SanDisk Technologies Inc.Inventors: Yongke Sun, Yingda Dong
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Patent number: 9342470Abstract: Methods for enabling software from a storage-capable device including the steps of: loading, by a host system operationally connected to the storage-capable device, software from an authenticatable storage area residing in the storage-capable device; validating the software; and installing the validated software, wherein the validated software provides an interface between the host system and the storage-capable device. In some embodiments, the software is enabling software, the method further including the step of loading, by the host system, device-functionality software from the authenticatable storage area. In some embodiments, the method further includes the steps of: validating the device-functionality software; and enabling the validated device-functionality software.Type: GrantFiled: October 14, 2013Date of Patent: May 17, 2016Assignee: SanDisk Technologies Inc.Inventors: Donald Ray Bryant-Rich, Judah Gamliel Hahn
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Patent number: RE46013Abstract: The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.Type: GrantFiled: April 2, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Robert D Selinger, Gary Lin, Paul Lassa, Chaoyang Wang
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Patent number: RE46014Abstract: Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.Type: GrantFiled: May 22, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies Inc.Inventors: Manabu Sakai, Toru Miwa
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Patent number: RE46023Abstract: Technology for replacing a first storage unit operatively coupled to a device is provided. Content of the first storage unit is sent to a new storage unit that serves as the replacement of the first storage unit. In one embodiment, the content is first sent to a trusted third-party server and then transferred from the server to the new storage unit. A portion of the content on the new storage unit is adjusted in one embodiment to maintain content security features that were implemented in the first storage unit. The upgrading can be performed under the control of a software entity that is installed on the device. In various embodiments, the first storage unit may be bound to a third storage unit prior to the upgrade process. In such cases, the process can include measures to bind the new storage unit to the third storage unit.Type: GrantFiled: April 2, 2014Date of Patent: May 31, 2016Assignee: SanDisk Technologies Inc.Inventors: Mei Yan, Robert C Chang, Farshid Sabet-Sharghi, Po Yuan, Bahman Qawami