Abstract: A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.

Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.

Abstract: Non-volatile memory structures for performing compute in memory inferencing for neural networks are presented. To improve performance, both in terms of speed and energy consumption, weight matrices are replaced with their singular value decomposition (SVD) and use of a low rank approximations (LRAs). The decomposition matrices can be stored in a single array, with the resultant LRA matrices requiring fewer weight values to be stored. The reduced sizes of the LRA matrices allow for inferencing to be performed more quickly and with less power. In a high performance and energy efficiency mode, a reduced rank for the SVD matrices stored on a memory die is determined and used to increase performance and reduce power needed for an inferencing operation.

Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g.

Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.

Abstract: An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine a slope error between the high temperature code and a low temperature code generated by the temperature sensor at the lowest temperature. Finally, determine a correction function that compensates for the slope error of measured temperature codes generated by the temperature sensor for temperatures across the qualification temperature range.

Abstract: Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of the array for the multiplication of the input with the weight. To perform a multiply and accumulate operation, the results of the multiplications are accumulated by adders connected to sense amplifiers along the bit lines of the array. The adders can be configured to multiple levels of precision, so that the same structure can accommodate weights and activations of 8-bit, 4-bit, and 2-bit precision.

Abstract: An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

Abstract: A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

Abstract: A non-volatile memory device includes arrays of non-volatile memory cells that are configured to the store weights for a recurrent neural network (RNN) inference engine with a gated recurrent unit (GRU) cell. A set three non-volatile memory arrays, such as formed of storage class memory, store a corresponding three sets of weights and are used to perform compute-in-memory inferencing. The hidden state of a previous iteration and an external input are applied to the weights of the first and the of second of the arrays, with the output of the first array used to generate an input to the third array, which also receives the external input. The hidden state of the current generation is generated from the outputs of the second and third arrays.