Patents Assigned to SanDisk Technologies
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Publication number: 20240105269Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Anirudh Amarnath, Aravind Suresh, Abhijith Prakash
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Publication number: 20240105271Abstract: Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Yanli Zhang, James K. Kai, Johann Alsmeier
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Publication number: 20240105262Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Ramy Nashed Bassely Said, Jiahui Yuan, Lito De La Rama
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Publication number: 20240105265Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Masaaki Higashitani, Abhijith Prakash, Dengtao Zhao
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Publication number: 20240103742Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Towhidur Razzak, Ravi Kumar, Abu Naser Zainuddin, Jiahui Yuan
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Patent number: 11942157Abstract: An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.Type: GrantFiled: March 17, 2022Date of Patent: March 26, 2024Assignee: SanDisk Technologies LLCInventors: Jiacen Guo, Xiang Yang, Xiaochen Zhu
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Publication number: 20240095233Abstract: Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality of supported interfaces is to be used to flush data from a processor complex.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: SanDisk Technologies LLCInventors: Nisha Talagala, Swaminathan Sundararaman, David Flynn
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Publication number: 20240096826Abstract: An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.Type: ApplicationFiled: September 19, 2022Publication date: March 21, 2024Applicant: SanDisk Technologies LLCInventors: Guangyuan Li, Yuji Totoki, Fumiaki Toyama
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Publication number: 20240096850Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Applicant: SanDisk Technologies LLCInventors: Jayavel Pachamuthu, Srinivasan Sivaram, Masaaki Higashitani
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Patent number: 11935593Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.Type: GrantFiled: May 25, 2022Date of Patent: March 19, 2024Assignee: SanDisk Technologies LLCInventors: Yi Song, Jiahui Yuan, Xiang Yang
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Patent number: 11935585Abstract: An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.Type: GrantFiled: October 25, 2021Date of Patent: March 19, 2024Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Arka Ganguly, Ohwon Kwon
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Publication number: 20240086074Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Applicant: SanDisk Technologies LLCInventors: Yi Song, Jiahui Yuan, Yanjie Wang
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Publication number: 20240087650Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Applicant: SanDisk Technologies LLCInventors: Han-Ping Chen, Guirong Liang
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Patent number: 11929125Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.Type: GrantFiled: June 23, 2021Date of Patent: March 12, 2024Assignee: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Chia-Kai Chou, Iris Lu
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Publication number: 20240079062Abstract: The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Jiacen Guo, Han-Ping Chen, Henry Chin, Guirong Liang, Xiang Yang
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Publication number: 20240079063Abstract: The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Han-Ping Chen, Yanjie Wang
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Publication number: 20240079061Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Xiaoyu Che, Yanjie Wang
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Publication number: 20240078028Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Chin-Yi Chen, Muhammad Masuduzzaman, Xiang Yang
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Publication number: 20240079068Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Applicant: SanDisk Technologies LLCInventors: Dengtao Zhao, Deepanshu Dutta, Peng Zhang, Heguang Li
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Publication number: 20240071482Abstract: Technology is disclosed herein for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify. The lockout verify saves considerable current and/or power. However, performing the lockout verify during the first programming phase may slow performance due to a need to scan the content in a remote set of data latches.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Hua-Ling Cynthia Hsu