Patents Assigned to SanDisk Technologies
  • Publication number: 20230420055
    Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yihang Liu, Xiaochen Zhu, Lito De La Rama, Feng Gao
  • Patent number: 11854592
    Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: December 26, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
  • Patent number: 11854620
    Abstract: An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: December 26, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Erika Penzo, Han-Ping Chen, Henry Chin
  • Publication number: 20230410912
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes. The control means is configured to select the transistor threshold voltage of the drain-side select gate transistors as a stable transistor threshold voltage for a grouping of the memory cells to minimize shifting of the transistor threshold voltage following a plurality of read operations of the memory cells. The control means is also configured to program the transistor threshold voltage of the drain-side select gate transistor of the plurality of memory holes associated with the grouping of the memory cells to the stable transistor threshold voltage.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Abhijith Prakash, Xiang Yang
  • Publication number: 20230410867
    Abstract: Wear levelling techniques based on use of a Galois field for the logical to physical translation of data addresses for a non-volatile memory, such as an MRAM-based memory, are presented. This not only provides a wear levelling technique to extend memory life, but also adds an additional layer of security to the stored memory data. More specifically, the following presents embodiments for secure wear levelling based on a Galois field having an order based on the size of the memory. To further improve security, a randomly generated rotation of the logically address based on the Galois field can also be used.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Martin Hassner, Mark Branstad
  • Publication number: 20230410911
    Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying withing the allowed peak Icc.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Towhidur Razzak, Jiahui Yuan, Deepanshu Dutta
  • Publication number: 20230410906
    Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Xiang Yang
  • Publication number: 20230410922
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Abhijith Prakash, Xiang Yang
  • Publication number: 20230410901
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Dong-Il Moon, Abhijith Prakash, Wei Zhao, Henry Chin
  • Publication number: 20230410921
    Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue, Hua-Ling Hsu
  • Publication number: 20230410923
    Abstract: A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: during a program loop for programming a set of states, select a first bitline biasing mode that dictates a scheme for biasing a first set of bitlines and apply the first bitline biasing mode before verifying the set of states. The controller further configured to during another program loop for programming another set of states, select a second bitline biasing mode that dictates a scheme for biasing a second set of bitlines and apply the second bitline biasing mode before verifying the other set of states.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Wei Zhao, Henry Chin
  • Publication number: 20230410920
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Han-Ping Chen, Wei Zhao, Henry Chin
  • Patent number: 11848059
    Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: December 19, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang, Abhijith Prakash
  • Publication number: 20230402110
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Ke Zhang, Ming Wang, Liang Li
  • Publication number: 20230402107
    Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian, Dmitry Vaysman
  • Publication number: 20230402099
    Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Ke Zhang, Liang Li, Ming Wang
  • Publication number: 20230402105
    Abstract: The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang
  • Patent number: 11842775
    Abstract: A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 12, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Nidhi Agrawal, Bo Lei, Zhenni Wan
  • Publication number: 20230395157
    Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Yanjie Wang
  • Patent number: 11837297
    Abstract: A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 5, 2023
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang