Abstract: Provided in the embodiments of the present disclosure are a method and apparatus for training an image reconstruction model, a storage medium, and an electronic device. The method includes: acquiring a target teacher image reconstruction model; training, by using the target sample image set, a student image reconstruction model to be trained, and ending the training until a target loss value satisfies a second preset loss condition, so as to obtain a target student image reconstruction model, wherein the target loss value is a loss value determined according to a first loss value and a second loss value, and the second loss value is a loss value determined according to a difference value between a predicted value and a real value respectively determined by the student image reconstruction model to be trained and the target teacher image reconstruction model.

Abstract: The present disclosure provides a full-duplex digital self-interference clear method, including: before a signal is transmitted with a peer device in a full-duplex mode, performing a calculation by a self-adaptive algorithm to obtain a pre-distortion processing coefficient; under the condition that the signal is transmitted with the peer device in the full-duplex mode, performing pre-distortion processing on a first signal sent by the transmit link to the peer device according to the pre-distortion processing coefficient to obtain a second reconstructed interference signal; and performing self-interference clear according to the second reconstructed interference signal and a second interference signal of the receive link, with the second interference signal being a signal obtained through superimposition of an interference signal generated by the first signal in the receive link and a second signal received by the receive link from the peer device.

Abstract: Provided are a multi-user multiple-input multiple-output detection method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: in a case where it is determined that received data includes data for first user equipment and data for at least one second user equipment, determining a first detection method according to a modulation mode of the first user equipment (100); and performing multi-user joint detection on the received data with the first detection method (101).

Abstract: Provided are a power amplification apparatus and a transmitter. The power amplification apparatus includes power amplification modules each including a voltage output unit and a power amplification unit; the voltage output unit outputs a first voltage signal (VIN_A) and a second voltage signal (VIN_B). The power amplification unit includes a selector (MUX), a radio frequency processing circuit, and a first switch transistor (M1), the radio frequency processing circuit processes a baseband signal to output a first radio frequency signal to a source of the first switch transistor (M1), and the selector (MUX) is configured to correspondingly strobe the first voltage signal (VIN_A) or the second voltage signal (VIN_B) according to an operating state of the first switch transistor (M1).

Abstract: Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.

Abstract: The present application relates to the field of communication technology, and discloses a packet forwarding method and device, and a computer readable storage medium. The packet forwarding method includes: determining a forwarding type of a packet, and acquiring configuration information corresponding to the forwarding type, the configuration information including a comparison type and an offset address of at least one set of comparators; configuring the at least one set of comparators according to the comparison type; acquiring a comparison data source of the at least one set of comparators according to the offset address; and determining a forwarding rule of the packet according to the comparison type of the at least one set of comparators as configured and the comparison data source of the at least one set of comparators as configured.

Abstract: A low-illuminance video processing method, a low-illuminance video processing device and a storage medium are disclosed. The method includes: acquiring a same number of preceding frame images and subsequent frame images corresponding to a current video frame of a low-illuminance video to obtain a frame image set corresponding to the current video frame, and performing traversal on the low-illuminance video to obtain frame image sets corresponding to all video frames; after performing image alignment on all frame images in the frame image sets corresponding to all video frames, inputting the frame image sets into a pre-trained low-illuminance image enhancement model to obtain enhanced frame images; and generating an enhanced video based on the enhanced frame images.

Abstract: The present application provides an antenna calibration method and apparatus, and a remote radio unit. The method includes: generating a calibration sequence of a channel to be calibrated; determining, according to obtained calibration configuration information of the channel to be calibrated and an output sequence of the channel to be calibrated, a calibration response sequence of the channel to be calibrated; and calibrating the channel to be calibrated according to the calibration response sequence of the channel to be calibrated and the calibration sequence of the channel to be calibrated.

Abstract: The present disclosure provides an interface data processing method, a transmitting-end device and a receiving-end device. The method includes: mapping data to be processed into interface data based on a data type of the data to be processed, a data type which a receiving-end device can process and preset block description information; and sending the interface data to the receiving-end device.

Abstract: Disclosed is a test apparatus, including: a connection circuit having a plurality of mounting positions each configured to connect a sample; a detection unit configured to perform a detection on the sample; and a control unit configured to control the detection unit to perform the detection on the sample. Further disclosed is a test method, including: connecting a sample to a mounting position of a test apparatus; and perform a test on the sample with the test apparatus.

Abstract: Embodiments of the present disclosure provide an amplitude and phase calibration method and device, a storage medium, and an electronic device. The method includes: receiving a plurality of signals to be calibrated, with the plurality of signals to be calibrated being signals of one or more digital channels; routing the plurality of signals to be calibrated to a plurality of basic units, with each of the basic units configured to process one of the signals to be calibrated; and performing amplitude and phase calibration on the plurality of signals to be calibrated by the plurality of basic units.

Abstract: The method includes: mapping determined transmission information and physical information about a downlink to N layers in a resource block (RB), so as to obtain N pieces of layer information, wherein N is a natural number greater than or equal to 1; modulating each of the N pieces of layer information to obtain N pieces of layer complex-value information; precoding each of the N pieces of layer complex-value information to obtain N pieces of RB antenna data, wherein the N pieces of RB antenna data are respectively mapped to N antenna ports; and sending the N pieces of RB antenna data.

Abstract: The present disclosure provides a linearity calibration method for digital time converter, including: acquiring a phase prediction parameter and a locked phase error, and calculating a control word of a digital time converter according to the phase prediction parameter, the locked phase error, a pre-configured nonlinear predistortion function, and a pre-configured calibration order n, with the control word being configured to enable the digital time converter to adjust a delay of a reference clock, so as to keep the reference clock and a feedback clock which are input to a time digital converter in a tracked state. The present disclosure further provides a linearity calibration apparatus for digital time converter and a digital phase lock loop.

Abstract: Disclosed are a pipelined successive approximation register analog-to-digital converter, an integrated circuit, and an electronic device. The pipelined successive approximation register analog-to-digital converter includes: a first-stage successive approximation register analog-to-digital converter (10), a residue amplifier (30), a second-stage successive approximation register analog-to-digital converter (20), and a digital coding unit (40).

Abstract: Disclosed are a time synchronization method, a time synchronization device, a time synchronization apparatus and a storage medium. The method includes: periodically generating, by a local device, a synchronization request signal, and determining a first reference ID of the local device; sending the synchronization request signal and the first reference ID to peer devices; receiving a second reference ID and time information sent from each peer device through a communication link; and updating time of the local device according to the time information transmitted from a calibration link, the calibration link being a corresponding communication link of a target reference ID in second reference IDs sent from the peer devices.

Abstract: Provided are a sampling circuit and a sampling method. The circuit comprises: a generator, configured to generate a first loopback pulse signal; a loopback selection module, configured to establish a plurality of loopback links according to a pre-configured connection combination; a link loopback pulse signal transmission module, configured to receive the first loopback pulse signal, and transmit the first loopback pulse signal in the plurality of loopback links; a loopback sampling module, connected to the link loopback pulse signal transmission module and configured to determine, from the plurality of loopback links, a target loopback link on which sampling is to be performed, and sample first link data that is on the target loopback link and passes through a target sampling point, and a sampling storage module, connected to the loopback sampling module and configured to store sampling data in a random access memory.

Abstract: The present disclosure provides an analog-to-digital conversion method applied to an analog-to-digital converter and including: for any clock cycle, amplifying, through an inter-stage gain amplifier, a first residual stored in a sampling capacitor corresponding to a first analog-to-digital conversion channel, and sampling the amplified first residual through a stage-2 sub-analog-to-digital converter corresponding to the first analog-to-digital conversion channel; sampling and quantizing an analog signal through a stage-1 sub-analog-to-digital converter, and storing an obtained second residual in a sampling capacitor corresponding to a second analog-to-digital conversion channel; and generating a digital signal according to output signals of the stage-1 and stage-2 sub-analog-to-digital converters; and for any two adjacent clock cycles, an analog-to-digital conversion channel serving as the second analog-to-digital conversion channel in a current clock cycle serves as the first analog-to-digital conversion cha

Abstract: Disclosed are an interposer and a chip package structure. The interposer may include: at least one signal transmission vias; at least one insulator isolation rings, one of said insulator isolation rings encircling one of said signal transmission vias; and at least one reverse-biased PN junction isolation rings, one of said reverse-biased PN junction isolation rings surrounding at least one of said insulator isolation rings, and the reverse-biased PN junction isolation ring including a semiconductor ring of a first conductivity type and a semiconductor ring of a second conductivity type from inside to outside, the semiconductor ring of the second conductivity type is connected to a bias potential.

Abstract: Provided in the present disclosure is a variable gain amplifier, including: a voltage signal input end; a high level generation module including two high level signal output ends, and configured to convert a voltage signal input from the voltage signal input end into a first high level signal and a second high level signal; a switch signal conversion module including a high level signal input end, N digital signal input ends and N switch signal output ends, and configured to output, through corresponding switch signal output ends and under the control of signals input from the digital signal input ends, gain control signals associated with a signal output from the first high level signal output end; and an amplification module including an amplification unit and N stages of gain control units, where N is a positive integer not less than 1. Further provided is a transmitting apparatus.

Abstract: A channel information processing method includes: generating a de-mapping related parameter of each CORESET and a first start parameter of each search space; generating a second start parameter of each CORESET; traversing each second start occasion, calculating index information of blind detection parameter and de-mapping related parameter, and storing the index information of the blind detection parameter and the de-mapping related parameter into a search space associated with the traversed second start occasion; traversing each search space, if a traversed search space is activated, updating a state of an activation flag in the second start occasion to an activated state; and sequentially traversing each second start occasion according to a time sequence, and in a case where the state of the activation flag in the traversed second start occasion is the activated state, reading the de-mapping related parameter and the blind detection parameter corresponding to the second start occasion.