Abstract: The present disclosure provides a chiplet, including: an inter-chiplet interconnect interface connected to one other chiplet, a selection module, and a processing module; the inter-chiplet interconnect interface receives second debugging information from the other chiplet; the selection module receives at least one piece of debugging information of the second debugging information, and send the at least one piece of debugging information to the processing module; and the processing module forwards, if the at least one piece of debugging information is debugging information for debugging of the chiplet, the at least one piece of debugging information within the chiplet for the debugging of the chiplet, and sends, if the at least one piece of debugging information is debugging information for debugging of the other chiplet, the at least one piece of debugging information to the inter-chiplet interconnect interface.

Abstract: A message processing method includes: obtaining frequency-domain in-phase quadrature (IQ) data according to uplink data, and storing the frequency-domain IQ data in a storage space; receiving a control plane message issued by an Open Radio Access Network Distributed Unit (O-DU), analyzing the control plane message to obtain a control plane parameter, and caching the control plane parameter in a queue corresponding to the control plane parameter in a queue group, M queues in the queue group stores control plane parameters of M symbols; reading the control plane parameter, and generating a user plane message transmission scheduling command according to the control plane parameter; reading the frequency-domain IQ data from the storage space according to the user plane message transmission scheduling command; and obtaining an uplink user plane message to be sent according to the read frequency-domain IQ data, and sending the uplink user plane message to the O-DU.

Abstract: The present disclosure provides a fronthaul message processing method, including: determining a type keyword of a fronthaul message according to a type of a transport layer for transmitting the fronthaul message; determining a type of the fronthaul message according to the type keyword; determining a position of service data carried by the fronthaul message according to the type of the fronthaul message; and extracting and processing the service data according to the position of the service data. The present disclosure further provides a fronthaul message processing apparatus, a fronthaul interface, a communication device, and a computer-readable storage medium.

Abstract: Provided are a signal processing method, an electronic device, and a storage medium. The signal processing method includes: acquiring control signal including a Time Division Duplex (TDD) signal (S110); adjusting time sequence of the TDD signal to target time sequence according to preset adjustment parameter (S120); and obtaining driving signal based on the TDD signal having the target time sequence, with the driving signal being for a Power Amplifier (PA) and a Low Noise Amplifier (LNA) (S130).

Abstract: Embodiments of the present application relate to the technical field of network communication, and disclose a method and a device for caching a message, an electronic equipment and a storage medium. The method for caching the message includes: dividing a cache space into an N*N cache array, N being a natural number greater than zero, and each cache block in the cache array being in a same size; selecting a cache block for storing the message according to a size of the message to be stored and a number of free addresses of each cache block; and storing the message in a free address of a selected cache block.

Abstract: The present disclosure provides a network anti-replay method and apparatus, an electronic device, and a storage medium. The method includes: according to a current packet number of a currently received data packet, determining a section to which the current packet number belongs in a replay window, with the replay window being divided into sections, and each section being configured to record packet numbers of L received data packets which belong to the section; and L being smaller than T, and T being a total number of packet numbers belonging to the section; and in a case where the current packet number is not coincident with packet numbers recorded in the determined section and the current packet number is not coincident with packet numbers of recently received N historical data packets, performing integrity authentication on the currently received data packet, with N being a natural number greater than 1.

Abstract: Embodiments of the present disclosure provide a packet matching method and apparatus, a storage medium, and an electronic device. The method includes: determining multiple Hash calculation results corresponding to a key value of a packet; indexing addresses in multiple counter groups respectively according to the multiple Hash calculation results, so as to determine multiple counters, wherein one counter is indexed in one counter group; determining one target counter from the multiple counters; acquiring a target entry at a corresponding position of an off-chip memory according to the address of the target counter; in a case where the target entry is equal to the key value, determining that the packet matches the target entry.

Abstract: Provided are a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. The differential latch circuit includes: a first-stage differential latch circuit (I), a second-stage differential inverter circuit (II), and a low-level shift circuit, a pull-up terminal of a differential positive terminal of the second-stage differential inverter circuit (II) includes a first P-Channel Metal-Oxide-Semiconductor (PMOS) transistor (M9) and a second PMOS transistor (M10), a pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit (II) includes a third PMOS transistor (M15) and a first N-Channel Metal-Oxide-Semiconductor (NMOS) transistor (M11), and a circuit structure of a differential negative terminal of the first-stage differential latch circuit (I) is symmetrical to a circuit structure of a differential positive terminal of the first-stage differential latch circuit (I).

Abstract: A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire1, a second interconnect parasitic resistor Rwire2, an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire1 and one end of the Rnet. The other end of the Rwire1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire2. A positive electrode of the Dio_die is connected to the other end of the Rnet.

Abstract: Disclosed are a signal processing circuit, a chip, a circuit board assembly and a radio-frequency transceiver, where the signal processing circuit may include a resistor array, a mixer, an ADC, a DAC and an amplifier. The resistor array has an output end connected to an input end of the mixer, and the ADC has an output end connected to an input end of the DAC; the resistor array has an input end connected to an input end of the ADC, an RF signal input end is formed at a connection of the input end of the resistor array and the input end of the ADC; the mixer has an output end connected to an output end of the DAC, and a residual signal output end for outputting a residual signal is formed at a connection of the output end of the mixer and the output end of the DAC.

Abstract: Provided in the embodiments of the present disclosure are a method and apparatus for training an image reconstruction model, a storage medium, and an electronic device. The method includes: acquiring a target teacher image reconstruction model; training, by using the target sample image set, a student image reconstruction model to be trained, and ending the training until a target loss value satisfies a second preset loss condition, so as to obtain a target student image reconstruction model, wherein the target loss value is a loss value determined according to a first loss value and a second loss value, and the second loss value is a loss value determined according to a difference value between a predicted value and a real value respectively determined by the student image reconstruction model to be trained and the target teacher image reconstruction model.

Abstract: The present disclosure provides a full-duplex digital self-interference clear method, including: before a signal is transmitted with a peer device in a full-duplex mode, performing a calculation by a self-adaptive algorithm to obtain a pre-distortion processing coefficient; under the condition that the signal is transmitted with the peer device in the full-duplex mode, performing pre-distortion processing on a first signal sent by the transmit link to the peer device according to the pre-distortion processing coefficient to obtain a second reconstructed interference signal; and performing self-interference clear according to the second reconstructed interference signal and a second interference signal of the receive link, with the second interference signal being a signal obtained through superimposition of an interference signal generated by the first signal in the receive link and a second signal received by the receive link from the peer device.

Abstract: Provided are a multi-user multiple-input multiple-output detection method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: in a case where it is determined that received data includes data for first user equipment and data for at least one second user equipment, determining a first detection method according to a modulation mode of the first user equipment (100); and performing multi-user joint detection on the received data with the first detection method (101).

Abstract: Provided are a power amplification apparatus and a transmitter. The power amplification apparatus includes power amplification modules each including a voltage output unit and a power amplification unit; the voltage output unit outputs a first voltage signal (VIN_A) and a second voltage signal (VIN_B). The power amplification unit includes a selector (MUX), a radio frequency processing circuit, and a first switch transistor (M1), the radio frequency processing circuit processes a baseband signal to output a first radio frequency signal to a source of the first switch transistor (M1), and the selector (MUX) is configured to correspondingly strobe the first voltage signal (VIN_A) or the second voltage signal (VIN_B) according to an operating state of the first switch transistor (M1).

Abstract: Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.

Abstract: The present application relates to the field of communication technology, and discloses a packet forwarding method and device, and a computer readable storage medium. The packet forwarding method includes: determining a forwarding type of a packet, and acquiring configuration information corresponding to the forwarding type, the configuration information including a comparison type and an offset address of at least one set of comparators; configuring the at least one set of comparators according to the comparison type; acquiring a comparison data source of the at least one set of comparators according to the offset address; and determining a forwarding rule of the packet according to the comparison type of the at least one set of comparators as configured and the comparison data source of the at least one set of comparators as configured.

Abstract: A low-illuminance video processing method, a low-illuminance video processing device and a storage medium are disclosed. The method includes: acquiring a same number of preceding frame images and subsequent frame images corresponding to a current video frame of a low-illuminance video to obtain a frame image set corresponding to the current video frame, and performing traversal on the low-illuminance video to obtain frame image sets corresponding to all video frames; after performing image alignment on all frame images in the frame image sets corresponding to all video frames, inputting the frame image sets into a pre-trained low-illuminance image enhancement model to obtain enhanced frame images; and generating an enhanced video based on the enhanced frame images.

Abstract: The present application provides an antenna calibration method and apparatus, and a remote radio unit. The method includes: generating a calibration sequence of a channel to be calibrated; determining, according to obtained calibration configuration information of the channel to be calibrated and an output sequence of the channel to be calibrated, a calibration response sequence of the channel to be calibrated; and calibrating the channel to be calibrated according to the calibration response sequence of the channel to be calibrated and the calibration sequence of the channel to be calibrated.

Abstract: Disclosed is a test apparatus, including: a connection circuit having a plurality of mounting positions each configured to connect a sample; a detection unit configured to perform a detection on the sample; and a control unit configured to control the detection unit to perform the detection on the sample. Further disclosed is a test method, including: connecting a sample to a mounting position of a test apparatus; and perform a test on the sample with the test apparatus.

Abstract: The present disclosure provides an interface data processing method, a transmitting-end device and a receiving-end device. The method includes: mapping data to be processed into interface data based on a data type of the data to be processed, a data type which a receiving-end device can process and preset block description information; and sending the interface data to the receiving-end device.