Abstract: Disclosed are an interrupt processing method and an interrupt controller. Before a CPU writes interrupt processing completion identification information of a current interrupt into an interrupt controller, interrupt source clear information of the interrupt is stored into the interrupt controller; and then when the interrupt controller receives a request, sent by the CPU, for writing the interrupt processing completion identification information, an interrupt source of the interrupt is directly cleared according to the interrupt source clear information stored in the interrupt controller, the CPU does not need to firstly access an interrupt clear register of a corresponding peripheral through a plurality of bus converter bridges to acquire information needed for clearing the interrupt source and then perform clearance.

Abstract: A counter includes: a computing module (100) and N counting modules (101). Each counting module includes a plurality of counting spaces corresponding to different counting entries, and counting spaces of the same counting entry in different counting modules have the same address, wherein the counting module is arranged to provide a value for computing to the computing module in response to a counting application of a counting application source. The computing module is arranged to read values of the same counting entry in different counting modules and accumulate the read values to obtain a total count value of the counting entry, N being an integer not less than 1. Also disclosed is a counting method.

Abstract: A method for traffic scheduling includes: authorizing a transmitting module to generate total authorization, allocating the total authorization to each stream queue according to weights preconfigured for each port and a stream queue mounted to each port, and transmitting the allocated authorization to a stream queue management module; the stream queue management module receiving data packets and storing the data packets in each stream queue, maintaining an authorization surplus barrel for each stream queue, storing the received authorization in the authorization surplus barrel of the stream queue, and if the authorization surplus and the queue depth in the authorization surplus barrel are greater than a preset threshold, notifying a scheduling module to output a data packet in the stream queue; and after receiving the notification from the stream queue management module, the scheduling module outputting a data packet in the stream queue according to a preset scheduling policy.

Abstract: Disclosed are a link control method and apparatus. The method includes that: link information and/or machine frame information in a system is acquired; and link control is performed according to the acquired link information and/or machine frame information. According to the technical solutions described in the disclosure, the problems of local congestion and packet loss in a three-level asymmetrical switching system can be effectively solved, the traffic level of the system is ensured, and the performance of the system is improved.

Abstract: Disclosed are a detection method and device for a digital intermediate frequency processing system. The method comprises: forming and transmitting excitation data to a digital intermediate frequency processing system; collecting detection data formed by processing the excitation data by the digital intermediate frequency processing system; and performing a bit-by-bit comparison on the detection data and reference data to form a detection result. Further provided is a computer storage medium.

Abstract: Disclosed is a chip-based data transmission method for a data sending side. The method includes that protocol layer processing is performed on input data, and the data after the protocol layer processing is mapped to each physical channel for transmission; meta-frame layer processing is performed on the data transmitted by each physical channel, and the data after the meta-frame layer processing is sent. Another chip-based data transmission method for a data receiving side is provided which includes that meta-frame layer processing is performed on data received by each physical channel, the data after the meta-frame layer processing is mapped to a protocol layer for transmission, and the protocol layer processing is performed on the data transmitted by the protocol layer, and the data after the protocol layer processing is sent. A chip-based data transmission device and system, and a computer storage medium are also provided.

Abstract: Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current Kth cycle, scheduling for the cell to be dequeued to be dequeued, acquiring the actual value of the number of splicing units occupied by the cell to be dequeued, and storing the cell to be dequeued in a register the same number of bits wide as a bus in a cell splicing manner, wherein determining that the cell to be dequeued can be dequeued is conducted in accordance with the fact that a first back pressure count value of the (K?1)th cycle is less than or equal to a first preset threshold value, and the first back pressure count value of the (K?1)th cycle is obtained in accordance with an estimated value of the number of the splicing units occupied when the previous cell to be dequeued is dequeued, the number of splicing units capable of being transmitted by the bus in each cycle, and a fi

Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.

Abstract: A method for implementing a configurable on-chip interconnection system. The method comprises: in an interconnection system, master devices set bit widths of bus identifiers of the master devices, wherein the bit widths of the bus identifiers of the master devices are the same (301); and in a memory access process, the mater devices interact, by means of interconnection matrices only, with slave devices according to the bus identifiers (302). Also provided are a system and apparatus for implementing the method, and a storage medium.

Abstract: Disclosed is a closed-loop clock calibration method, comprising: performing clock calibration according to a calibration factor of an nth calibration period within the nth calibration period, and obtaining a calibration error of the nth calibration period; and according to the calibration error and calibration factor of the nth calibration period, obtaining a calibration factor of an (n+1)th calibration period, n being a positive integer. Also disclosed are a terminal and a computer storage medium.

Abstract: Disclosed is a DC offset cancellation (DCOC) method, comprising: after a receiver is electrified, acquiring a digital signal of an offset voltage at a circuit output port in the receiver, obtaining a digital control signal for controlling a DCOC output stage from the digital signal, and outputting, by the DCOC output stage, a current to a corresponding circuit of the receiver according to the digital control signal. Also disclosed is a DC offset cancellation device.

Abstract: Disclosed are a frequency offset estimation method and apparatus in an optical transmission network and a storage medium. The method comprises: acquiring a data symbol to be frequency offset estimated, and eliminating a noise phase, a phase generated by a light source and an information phase in the data symbol to be frequency offset estimated; and performing a correlation operation on a data symbol with a set interval in the data symbol after the elimination processing and using a correlation operation result to determine a frequency offset estimation value.

Abstract: A method for processing data based on 3072-point Fast Fourier Transform (FFT) and a processor based on 3072-point FFT are provided. The method for processing data based on 3072-point FFT includes: storing 3072-point data into a data storage module according to a predetermined mapping relationship (101); reading 16 data in parallel from the data storage module for performing 3-point DFT operation, and storing results into the data storage module in situ after completion of the operation (102); and reading 32 data in parallel from the data storage module for performing 1024-point DFT operation and storing results into the data storage module in situ after completion of the operation until the FFT of 3072-point data is completed (103).

Abstract: The disclosure discloses a Chromatic Dispersion (CD) detection method for an optical transmission network. Data of two polarization states orthogonal to each other is converted from time-domain data to frequency-domain data, extraction is performed on the frequency-domain data and a linear combination operation is performed on the extracted frequency-domain data, an argument of a CD value of the data of the two polarization states are obtained according to a result of the linear combination operation, and the CD value is estimated according to the argument of the CD value of the data of the two polarization states. The disclosure further discloses a CD detection device for the optical transmission network and a storage medium.

Abstract: A method for implementing interface cache dynamic allocation is disclosed in the present invention. The method includes: setting, in advance or when a system is running, the corresponding relationship between a free cache block and an interface required to be accessed in the application, and then sending data packets inputted from the interface to the cache block; when the system is running, if the interface required to be accessed needs to be increased, revoked or modified, adjusting the corresponding relationship between the changed interface and the corresponding cache block in real time. A device and computer storage medium for implementing the method are also disclosed in the present invention.

Abstract: Provided are a data error correcting method and device, and computer storage medium, the method comprising: respectively setting an index number for each data bit, and generating a first check code according to the index number; and generating a second check code according to the first check code, comparing the first check code with the second check code to determine an erroneous data bit, and correcting the erroneous data bit. The device comprises: a setting module configured to respectively set the index number for each data bit; a first check code generation module configured to generate the first check code according to the index number; a second check code generation module configured to generate the second check code according to the first check code; and a data processing module configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit.

Abstract: A clock recovery method is provided. The method has the following operations: performing clock balance pre-filtering on an input time/frequency domain signal according to a self-adaptive balance coefficient input currently, to obtain a balance pre-filtering signal; according to the balance pre-filtering signal, acquiring a phase error of the input time/frequency domain signal; and performing phase adjustment on the input time/frequency domain signal according to the phase error, and outputting a new self-adaptive balance coefficient after self-adaptive balance processing is performed on the phase-adjusted time/frequency domain signal. A clock recovery device and system and a non-transitory computer-readable storage medium are also provided.

Abstract: Provided is a token-bucket-based rate limiting method and apparatus, and a computer storage medium. The method includes that: network node equipment acquires a token bucket parameter according to an attribute of a message, then obtains a current token amount according to a time threshold and the token bucket parameter, compares the current token amount with a current message length, and processes the message according to a comparison result.

Abstract: Disclosed are a method and a system for scheduling a task in cloud computing. The feature information of the task is parameterized; the task is classified; the best working node is obtained by computation through a Bacteria Foraging Optimization Algorithm (BFOA) according to the classification result; and the best working node is matched with the task. Obviously, the BFOA is adopted to implement task scheduling and resource allocation in cloud computing, so that the cloud computing has the advantages of group, intelligent and parallel search, simplicity in escaping from a local minimum and the like for the scheduling of a user task group, is favourable for keeping the diversity of the task group in the cloud computing, can meet the requirement of the user better, and improves the degree of satisfaction of user experience.

Abstract: Disclosed is a layout method for a base station, including that a Base Transceiver Station/Base Station (BTS/BS) locates coordinates of a hotspot area range of a User Equipment (UE) and current coordinates of a micro cell, the BTS/BS dynamically schedules the micro cell according to the coordinates of the hotspot area range of the UE and the current coordinates of the micro cell and the BTS/BS dynamically coordinates the micro cell. Also disclosed are a layout system for a base station and a computer storage medium.