Patents Assigned to Santa Clara
  • Patent number: 9373769
    Abstract: A solar energy heat to electricity conversion device is provided that includes a thermally conductive solar receiver having a cylinder with an open end and a cup-shape closed end and a thermally conductive fin disposed on an outside surface of the cup-shape closed end, where the thermally conductive solar receiver is capable of absorbing solar energy directed into the cylinder, a thermoelectric module (TEM) that includes a first plate and a second plate, where the first plate is in contact with a surface of the thermally conductive fin, where the conductive fin is capable of transferring heat to the first plate, and a thermally conductive water block in contact with the TEM that is capable of cooling the TEM, where the water block includes a fluid input and a fluid output, where the TEM generates electricity according to a temperature difference between the first plate and the second plate.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 21, 2016
    Assignee: Santa Clara University
    Inventors: Hohyun Lee, Claire Kunkle, Mark F. Wagner, Rachel Donohoe
  • Patent number: 9307237
    Abstract: A video codec comprising a processor configured to generate a prediction block for a chroma block, wherein the prediction block comprises a predicted chroma sample, wherein the predicted chroma sample is based on a filtered reconstructed luma sample located in a corresponding reconstructed luma block, a plurality of downsampled filtered reconstructed luma samples located in positions neighboring the corresponding reconstructed luma block, and a plurality of downsampled chroma samples located in positions neighboring the chroma block.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: April 5, 2016
    Assignees: Futurewei Technologies, Inc., Santa Clara University
    Inventors: Lingzhi Liu, Guichun Li, Nam Ling, Jianhua Zheng, Philipp Zhang, Li Song
  • Patent number: 9179148
    Abstract: A method comprising receiving a plurality of reference pixels, computing a plurality of filter coefficients based on differences between a reference pixel and neighboring reference pixels in the plurality of reference pixels, and combining the filter coefficients with the reference pixel and the neighboring reference pixels to generate a filtered value, wherein the filtered value is used for intra prediction.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: November 3, 2015
    Assignees: Futurewei Technologies, Inc., Santa Clara University
    Inventors: Guichun Li, Lingzhi Liu, Changcai Lai, Nam Ling, Jianhua Zheng, Chen-Xiong Zhang
  • Patent number: 9093587
    Abstract: A motion controlled tracking mount is provided that includes a lateral rail perpendicular to a longitudinal rail, a first translation element slides on the lateral rail and a second translation element slides on the longitudinal rail and slides onto the lateral rail, a first rotatable connector attached to the first translation element and a second rotatable connector attached to the second translation element that rotate about axes perpendicular to the lateral and longitudinal rails, an apparatus mount with a distal region pivotably connected to the second rotatable connector, where the pivotable connection axis is parallel to a lateral dimension of the mount, and a linkage with a proximal end pivotable connected to the first rotatable connector and a distal end is pivotably connected to a proximal region of the mount, where an axis of the pivotable connection at the distal end is parallel to the lateral dimension of the mount.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: July 28, 2015
    Assignee: Santa Clara University
    Inventors: Matthew Neber, Hohyun Lee, Laughlin Barker, Criselle G. Olaes, Darcy Marumoto, Joseph Valdez
  • Publication number: 20150049807
    Abstract: There is disclosed a method, device and computer-readable storage medium for decoding video data. The method includes: obtaining a reference sample array of a video block; obtaining a sum of the reference sample array; calculating a threshold by performing arithmetic right shift to the sum, a shift value of the arithmetic right shift being determined according to size information of the video block; and determining the binary partition pattern by comparing the reference sample array with the threshold.
    Type: Application
    Filed: July 18, 2014
    Publication date: February 19, 2015
    Applicants: SANTA CLARA UNIVERSITY, FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Zhouye GU, Jianhua ZHENG, Nam LING, Philipp ZHANG
  • Publication number: 20140307787
    Abstract: There is disclosed a method, apparatus and computer program product for prediction mode selection for coding a block of a depth map. An ordered list of coding modes is obtained, wherein the ordered list of coding modes comprises a plurality of coding modes. And whether a depth modeling mode and/or a region boundary chain mode is to be added into the ordered list of coding modes in accordance with a decision condition is determined.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 16, 2014
    Applicants: Santa Clara University, Futurewei Technologies, Inc.
    Inventors: Jianhua ZHENG, Zhouye GU, Nam LING, Philipp ZHANG
  • Patent number: 7857849
    Abstract: A material that can be applied as implants designed to artificially replace or augment the cornea, such as an artificial cornea, corneal onlay, or corneal inlay (intrastromal lens) is provided. The artificial corneal implant has a double network hydrogel with a first network interpenetrated with a second network. The first network and the second network are based on biocompatible polymers. At least one of the network polymers is based on a hydrophilic polymer. The artificial cornea or implant has epithelialization promoting biomolecules that are covalently linked to the surface of the double network hydrogel using an azide-active-ester chemical linker. Corneal epithelial cells or cornea-derived cells are adhered to the biomolecules. The double network has a physiologic diffusion coefficient to allow passage of nutrients to the adhered cells.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: December 28, 2010
    Assignees: The Board of Trustees of the Leland Stanford Junior Iniversity, Santa Clara University
    Inventors: David Myung, Jaan Noolandi, Alan J. Smith, Curtis W. Frank, Christopher Ta, Yin Hu, Won-Gun Koh, Michael R. Carrasco
  • Patent number: 7650077
    Abstract: An optical transceiver module includes an optical-to-electrical converter configured to convert a first optical signal to a first electric signal, a first amplifier configured to amplify the first electric signal, a bandwidth controller coupled to the first amplifier, configured to control the frequency response characteristics of the amplification of the first amplifier to produce a first amplified electric signal, a driver circuit configured to receive a second electric signal and to produce a second amplified electric signal in response to the second electric signal and an optical feedback signal, an electrical-to-optical converter coupled to the micro-controller and configured to convert the second amplified electrical signal to a second optical signal, and a photo diode configured to detect the second optical signal and to produce the optical feedback signal to be received by the driver circuit.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: January 19, 2010
    Assignee: Source Photonics Santa Clara, Inc.
    Inventors: Rangchen Yu, Yuanjun Huang, Mingshou He, Bin Wei, Jiang Tian
  • Patent number: 7329831
    Abstract: Improved systems and methods for laser trimming resistors printed on a substrate layer are provided. An exemplary embodiment measures a resistance value for each annular resistor and sorts the annular resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 12, 2008
    Assignee: HADCO Santa Clara, Inc.
    Inventors: Nicholas Biunno, Atul Patel, Ken Ogle, George Dudnikov
  • Patent number: 7297896
    Abstract: Improved systems and methods for laser trimming resistors are provided. An exemplary embodiment measures a resistance value for each resistor and sorts the resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: November 20, 2007
    Assignee: HADCO Santa Clara, Inc.
    Inventors: Nicholas Biunno, Atul Patel, Ken Ogle, George Dudnikov
  • Patent number: 6972391
    Abstract: Improved systems and methods for laser trimming annular resistors printed on a circuit board are provided. An exemplary embodiment measures a resistance value for each annular resistor and sorts the annular resistors into one or more bins based on the measured resistance values and target resistance values associated with each annular resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each annular resistor with their respective target value. The laser drill uses laser trim files to trim the annular resistors within each bin in accordance with a laser trim file assigned to that bin.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: December 6, 2005
    Assignee: HADCO Santa Clara, Inc.
    Inventors: Nicholas Biunno, Atul Patel, Ken Ogle, George Dudnikov
  • Patent number: 6854922
    Abstract: A locking cover is provided for a manhole or other access opening formed in a soffit or the like, such as an access manhole formed in an otherwise enclosed overhead cell or chamber within a concrete overpass or bridge structure of a light rail or highway transportation system. The locking cover includes an upper section defined by multiple segments sized to fit upwardly through the manhole and then assemble to define a peripheral rim for seating upon an upper soffit surface generally circumscribing the manhole. A lower section includes a peripheral rim for substantially seated engagement with a manhole-circumscribing lower soffit surface, and carries a lock unit for releasible connection with a lock bolt depending from the assembled upper section. The lock unit is positioned within an access-restricting containment sleeve to resist and/or discourage tampering.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: February 15, 2005
    Assignee: Santa Clara Valley Transportation Authority, a public agency
    Inventor: Curtis D. Nicks
  • Publication number: 20040095398
    Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.
    Type: Application
    Filed: July 2, 2003
    Publication date: May 20, 2004
    Applicant: Intel Corporation, a Santa Clara Corporation
    Inventors: Richard D. Muratori, Myles J. Wilde, Donald F. Hooper
  • Publication number: 20040038481
    Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.
    Type: Application
    Filed: August 27, 2003
    Publication date: February 26, 2004
    Applicants: Siliconix Incorporated, Siliconix Incorporated, Santa Clara, Ca.
    Inventor: Mohamed N. Darwish
  • Patent number: 6282782
    Abstract: A method of forming a subassembly for use in a printed circuit board is described. This method includes providing a subassembly including a circuit board layer laminated to two sheets of conductive material with two intermediate sheets of prepreg material, forming a via in the assembly, plating the via, filling the via with a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. Also described is a method of forming a partially filled via in a circuit board layer and a method of forming a thermally conductive plug in a circuit board layer for the transfer of thermal energy from one surface of the circuit board to the other.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: September 4, 2001
    Assignee: Hadco Santa Clara, Inc.
    Inventors: Nicholas Biunno, Scott Bryan, Mason Hu
  • Patent number: 6276055
    Abstract: A method of forming one or more plugs in a circuit board layer is described which includes providing the circuit board layer, the circuit board layer having a first surface, a second surface, and defining a via containing a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. A product made according to the above method is also described.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: August 21, 2001
    Assignee: Hadco Santa Clara, Inc.
    Inventors: Scott K. Bryan, Nicholas Biunno
  • Patent number: 5870274
    Abstract: An in situ method for forming a bypass capacitor element internally within a PCB including the steps of arranging one or more uncured dielectric sheets with conductive foils on opposite sides thereof and laminating the conductive foils to the dielectric sheet simultaneously as the PCB is formed by a final lamination step, the conductive foils preferably being laminated to another layer of the PCB prior to their arrangement adjacent the dielectric sheet or sheets, the dielectric foils even more preferably being initially laminated to additional dielectric sheets in order to form multiple bypass capacitive elements as a compound subassembly within the PCB. A number of different dielectric materials and resins are disclosed for forming the capacitor element.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: February 9, 1999
    Assignee: Hadco Santa Clara, Inc.
    Inventor: Gregory L. Lucas
  • Patent number: 5682295
    Abstract: A reinforcement structure to protect an integrated circuit module located within a smart card. The smart card has two semi-rigid layers, with a first opening through the first layer located below the second layer. The reinforcement structure, which has a modulus of elasticity higher than the modulus of elasticity of the smart card, has a first portion extending through the first opening and a second portion extending over the upper surface of the first card layer. The integrated circuit module is positioned in the second card layer and is separated from the reinforcement structure by the second card layer. The reinforcement structure, which can have various shapes, relives stress on the integrated circuit module during bending and torsion of the card.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: October 28, 1997
    Assignees: US3, Inc., Santa Clara, Inc.
    Inventors: Charles F. Horejs, Jr., Thomas H. Templeton, Jr.
  • Patent number: 5226242
    Abstract: The present invention provides a vapor processing apparatus in which the vapor is generated in a region adjacent to the vapor processing area. This is generally done in a batch process and a limited volume of processing vapor is generated for each batch. The separation of the vapor generation from the processing avoids the contamination of the vapor source and the inadvertent cooling of the vapor generating area. In the preferred embodiment, two vessels are disposed one inside the other such that a vapor generating region is provided in the annular space between vessels. The vapor is injected into the processing region through channels formed in the annular space. In a preferred embodiment, the vapor is isopropyl alcohol and the substrates for processing are silicon wafers.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: July 13, 1993
    Assignee: Santa Clara Plastics, division of Preco, Inc.
    Inventor: Robert S. Schwenkler
  • Patent number: D594455
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: June 16, 2009
    Assignee: Source Photonics Santa Clara, Inc.
    Inventors: Zhong Yang, Zili Wang, Linhua Zhang, Dongsheng Li