Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.

Abstract: The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core.

Abstract: A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions.

Abstract: A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration.

Abstract: A flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten.

Abstract: Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.

Abstract: A flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten.

Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.

Abstract: An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.

Abstract: The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core.

Abstract: The apparatus and methods allow random hardware failure emulation of an integrated circuit (IC) by emulation of potential defects to enable behavior evaluation of the rest of the design in such situation. This emulation can non-intrusively address multiple points of failure. The emulation is performed in a pseudo-functional mode in order to evaluate the IC behavior in its standard functional mode. The system allows creation of a failure, and tracking both the detection of this failure and the required time for this detection. The system further allows generation of a failure in different points of the IC, on a single or multipoint failure approaches. Failure detection and correction mechanisms for a product life cycle are therefore provided. In an embodiment the system checks the conformity of the safety function of an IC, and makes sure the safety control logic behaves as expected in case of data corruption in any register.

Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

Abstract: An apparatus on an integrated circuit, and method thereof, provides a real-time flexible interface between inputs from a vehicle components and outputs to the vehicle control components. The functions comprises of a programmable interconnection matrix, engine sensors and a control interface. Both engine sensors and control functions comprise of fixed hardwired functions and a customization hardware area. The apparatus therefore provides means for flexible powertrain events control target for the next generation of low-polluting power trains of vehicles.

Abstract: An apparatus on an integrated circuit, and method thereof, provides a real-time flexible interface between inputs from a vehicle components and outputs to the vehicle control components. The functions comprises of a programmable interconnection matrix, engine sensors and a control interface. Both engine sensors and control functions comprise of fixed hardwired functions and a customization hardware area. The apparatus therefore provides means for flexible powertrain events control target for the next generation of low-polluting power trains of vehicles.

Abstract: An apparatus, protocol and methods for reducing vehicle energy consumption and for precise electronic event control, by implementing full CPU off-loading, using pulse-width modulation (PWM) with analog feedback diagnosis enabling real-time operation. Accordingly, analog feedback is used for external integrated circuits (IC) controlled by a PWM output, for processes to be analyzed. The apparatus includes a microprocessor that integrates an autonomous PWM module and an analog-to-digital converter (ADC) group manager, each including register modules for enabling analog-to-digital signal conversion comparisons of PWM feedback data, and generating of an interrupt command when required, and more specifically to automatically initiate transfer of data from the ADC to memory responsive of an interrupt trigger. As may be necessary the output of the ADC is calibrated or otherwise scaled to enable proper operation.

Abstract: An apparatus on an integrated circuit provides a real-time flexible interface between inputs from a vehicle components and outputs to the vehicle control components. The functions comprises of a programmable interconnection matrix, engine sensors and a control interface. Both engine sensors and control functions comprise of fixed hardwired functions and a customization hardware area. The apparatus therefore provides means for flexible powertrain events control target for the next generation of low-polluting power trains of vehicles.

Abstract: An apparatus on an integrated circuit provides a real-time flexible interface between inputs from a vehicle components and outputs to the vehicle control components. The functions comprises of a programmable interconnection matrix, engine sensors and a control interface. Both engine sensors and control functions comprise of fixed hardwired functions and a customization hardware area. The apparatus therefore provides means for flexible powertrain events control target for the next generation of low-polluting power trains of vehicles.

Abstract: An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.

Abstract: An apparatus, protocol and methods for reducing vehicle energy consumption and for precise electronic event control, by implementing full CPU off-loading, using pulse-width modulation (PWM) with analog feedback diagnosis enabling real-time operation. Accordingly, analog feedback is used for external integrated circuits (IC) controlled by a PWM output, for processes to be analyzed. The apparatus includes a microprocessor that integrates an autonomous PWM module and an analog-to-digital converter (ADC) group manager, each including register modules for enabling analog-to-digital signal conversion comparisons of PWM feedback data, and generating of an interrupt command when required, and more specifically to automatically initiate transfer of data from the ADC to memory responsive of an interrupt trigger. As may be necessary the output of the ADC is calibrated or otherwise scaled to enable proper operation.