Abstract: In one embodiment, a telephone system that includes a number of payphones intended for communication with servers via at least one communication network is disclosed. In one embodiment, the communication network includes a communication interface able to monitor communications between the said payphones and at least a first group of servers.

Abstract: An IC card system for a game machine using an IC card includes a game token input device for inputting a game token onto the IC card based on the amount of money deposited. The IC card system also includes a game device that decreases the number of game tokens stored on the IC card when the IC card is used with the game device. The IC system also includes a totaling device that determines the number of tokens inputted by the game token input device and the number of tokens used by the game devices, at a particular location.

Abstract: An integrated circuit device is disclosed. The device includes an active film having a semiconducting material and an integrated circuit disposed on an active face of the active film. The integrated circuit includes a plurality of circuit elements. In addition, the device includes an additional film fixed to the active face of the active film, the additional film at least partially covering said integrated circuit, and an anti-fraud mechanism disposed within the additional film, the anti-fraud mechanism being positioned to align with one of the plurality of circuit elements. In some aspects, the additional film includes a protective sub-film and a sealing sub-film, wherein the protective sub-film is sealed to the active face of the active film by the sealing sub-film.

Abstract: A contactless memory card that includes a card body (1), an integrated circuit (3) embedded in the card body, and a coupling antenna (4) connected to two contact pads (6) of the integrated circuit. The antenna is made in a spiral pattern, with its turns passing over the flush face (5) of the integrated circuit.

Abstract: The printed circuit has connection pads emerging in a face of the integrated circuit, which face is covered in an insulating layer (5) having openings in register with the connection pads, and at least one conductor track (7) extending over the first insulating layer and having one end connected to one of the connection pads of the integrated circuit. A second insulating layer (8) covers the first insulating layer and has openings (9) in register with each conductor track (7) of the first layer and in register with each connection pad that is not connected to a conductor track (7), and it carries at least one repositioning conductor track (10) extending over the second insulating layer (8) having one end connected to a conductor track (7) of the first insulating layer.

Abstract: An improved method and apparatus for classifying triangles. A description of a triangle in the form of the coordinates of its vertices is supplied to calculation logic. The calculation logic calculates a plurality or parameters of the triangle from these coordinates. These parameters are then provided to a look-up table. The look-up table has previously been programmed to include at each address the proper triangle classification for that address, with each address being a different combination of the parameters. The addresses for the look-up table cover all possible combinations of the parameters, and thus all possible triangles.

Abstract: A method for directly measuring the area of a topological surface with an arbitrary boundary shape lying in a fixed elevation different from a fixed surrounding surface elevation relies upon binocular stereo vision. Three stereo correlation measurements are made, one over a window entirely within the surface of interest, a second over a window outside the surface of interest and within the surrounding area, and a third over a window fully containing the surface of interest as well as some of the surrounding area. The correlation measured in the third case is the linear sum of the correlation value over each of the first two cases weighted by the proportion of the window that the two surfaces occupy.

Abstract: A system for shape recognition includes a spatial convolution filter which has an approximately band pass response. The filter is applied to a camera image and the sign of the filter's output is used to produce a second binary image. At sufficiently coarse (low center spatial frequency) scales, this image tends to change isolated shapes into single blob-shaped regions. The same convolution operator is then reapplied to this binary signal blob image and peaks in the output of the second convolution are used as the primitive elements for building a shape description. By processing the image with operators of two different scales the peaks shift position. The location of peaks from the coarse scale operator together with vectors to the fine scale peaks provide a description of the shape for a look-up table or other system.

Abstract: A system for clipping polygons representing three-dimensional objects to produce a representation of the portion of the objects in a desired viewing space is disclosed. A guardband space at least partially enclosing the viewing space is defined. The polygons are compared to the guardband space to determine which polygons intersect at least one of the guardband planes defining the guardband space. The intersecting polygons are also compared to the viewing space to determine if they intersect at least one of the viewing planes defining the viewing space. Only polygons intersecting both a viewing plane and a guardband plane are clipped.

Abstract: A graphic processing system for representing three-dimensional objects on a monitor which uses a pipeline of polygon processors coupled in series. The three-dimensional objects are converted into a group of two-dimensional polygons. These polygons are then sorted to put them in scan line order, with each polygon having its position determined by the first scan line on which it appears. Before each scan line is processed, the descriptions of the polygons beginning on that scan line are sent into a pipeline of polygon processors. Each polygon processor accepts one of the polygon descriptions and stores it for comparison to the pixels of that scan line which are subsequently sent along the polygon processor pipeline. For each new scan line, polygons which are no longer covered are eliminated and new polygons are entered into the pipe. After each scan line is processed, the pixels can be sent directly to the CRT or can be stored in a frame buffer for later accessing.

Abstract: A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing signals representing leading edge and trailing edge markers precisely within each period. The period circuit comprises a period-end memory having a plurality of storage locations which are addressed by a modulo(n) counter. To support multiple timing sets, or timing cycles, one or more of the most significant bits of the address field for the period-end memory may be reserved for designating each timing signal. The time interval measured by the period-end memory may be selectively extended by delaying the clocking signal used for incrementing the modulo(n) counter.

Abstract: A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

Abstract: A system for determining the s-plane parameters, s.sub.i and r.sub.i, of the transient response, ##EQU1## of a network-under-test (NUT). A filter bank, including N serially connected filter elements, has an input port and N output ports being the output ports of the filter elements. The system includes circuitry for sampling the response signal, at the N filter bank output ports. T seconds after a transient signal is received at the input port. A processor utilizes the values of the sampled response signal to determine the values of s.sub.i and r.sub.i.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: A video stream processing system comprising a novel modular family of image processing and pattern recognition submodules, the submodules utilize a unique system signalling and interface protocol, and thus can be cascaded and paralleled to produce complex special purpose image processing systems which can operate at video or near video data rates. A stream of digitized pixel data is pipelined through a variety of submodules to support a wide variety of image processing applications. A common video interface provides for handling pixel data in the video signal path and a processor interface allows communication to any modern microprocessor for overall system control, for optional addition image processing and for defining options within each submodule.

Abstract: A method for determining the transfer function of a data acquisition system involves inputting a set of bilevel input test patterns to the system and measuring the system's response. The input test patterns from a complete orthogonal set. The input test patterns or the system's response can be weighted to correct for aliasing error and/or to represent any arbitrary input waveform. From the ratio of the Fourier transform of the sum of the responses to the Fourier transform of the sum of the input test patterns the transfer function is derived. In operation, the transfer function is used to accurately determine the characteristics of any input waveform to the system.

Abstract: A region defining technique for use with a computer aided design system, including a geometry specification step and a loop-chasing step which together locate the complete set of sequences of linked elements which defines the inner and outer boundaries of the region of interest in response to a single user input identifying which region is of interest. The technique permits a user with a single "pick" to select a desired region of the display for further processing such as cross-hatching or extrusion, and provides a variety of useful applications not previously offered in commercially available computer aided design systems.

Abstract: A video stream processing system frame buffer controller for controlling external dynamic random access memory (DRAM) of a frame buffer and interfacing to the video stream processing signal bus. The frame buffer controller has four interfaces, video input interface, video output interface, memory interface and processor interface. The circuit can input image data from a camera and store the frames in external DRAM. The circuit provides for external processor access to pixels in the frame buffer and for output of the frame or portions of the frame, as well as output of frames in a format of CRT display and external DRAM refresh.

Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.

Abstract: An improved computer memory system based on a novel four transistor memory cell and an improved address decoder circuit is disclosed. The memory cell can be fabricated using currently available logic fabrication processes and requires a silicon area less than that required by prior art static memory cells. The improved decoder can be fabricated in significantly less silicon area than existing NOR gate decoder arrays and is faster than existing NOR gate decoder arrays.