Abstract: An image processing system for computing morphological characteristics of object regions in a binary image frame. The characteristics are generated at the frame rate. One embodiment utilizes an architecture including an interconnected delay component, bit packing component and LUT. The output values provided by the LUT are accumulated over one frame cycle to compute morphological characteristics.

Abstract: A high precision analog to digital converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compensate for errors of any bit combination. In a specific embodiment employing feedback compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a video camera. The processing of a frame of image data by each circuit component is simulated and the resulting frames of image data are stored until they are no longer needed by other components. The output of the simulated circuit is displayed on a monitor.The timing of the circuit is analyzed for distinct groups of components which must operate in synchronism. Scaling factors are calculated for each net in the group from the incremental scaling rate of each component and the connectivity of the circuit. The scaling factors indicate the relative rate at which value pixels arrive at each net. The time at which a reference pixel arrives at each net is then computed to ensure that corresponding pixels arrive together at components with multiple inputs.

Abstract: An arithmetic logic system for performing a variety of arithmetic and logical functions on pixel input streams such as averaging down the input image stream, computation of absolute values, and signed or unsigned, clipped or unclipped, addition, subtraction and multiplication. The arithmetic logic system has a first arithmetic logic unit connected to a plurality of input signals. A second arithmetic logic unit is coupled to the first arithmetic logic unit and operates on the output of the first arithmetic logic unit. A control unit is coupled to the first and second arithmetic logic units and controls the operation of the second arithmetic logic unit based on the output of the first arithmetic logic unit.

Abstract: A processing element may be used either separately or in an array of similar processing elements for performing concurrent data processing calculations. The processing element includes a multiported memory unit for storing data to be processed by any of a plurality of function units which are connected to the multiported memory unit. The multiported memory unit includes a number of data storage slots for storing data words to be processed and the results of said processing. Each function unit performs a calculation having as its inputs one or or more data words from the multiported memory unit. The result of this calculation is stored back in the multiported memory unit. The transfer of data to and from the function units is accomplished by use of the ports on said multiported memory unit. The data manipulated by the processing element is controlled by specifying a correspondence between data storage slots, memory input ports and memory output ports.