Abstract: A tri-state pin driver is formed in part, along with a pin sensor, on an integrated circuit. A pin driver and sensor are coupled to a common pin of a device under test. In normal mode, the pin driver drives a test signal. In high impedance mode, the pin driver is at a high impedance, enabling a sensor to monitor a response signal. The pin driver includes a driver stage formed off-chip by a pair of power transistors operated in the active region. The large power transistors enable a large current (i.e., +/-500 mA) to be sourced or sunk so as to drive a device under test and back-drive preceding circuits. Operating in the active region enables faster logic state transition times, and thus, a fast test rate, while reducing undesirable signal distortion. A predriver stage is configured as a unity-gain emitter follower. The predriver stage includes first and second signal paths. Each signal path includes a pair of transistors configured, during normal mode, as a transmission gate.

Abstract: Methods and apparatus are disclosed for conditional acquisition of potential measurements in integrated circuits, with the aid of electron-beam probes. The conditional acquisition enables display of waveform images which permit diagnosis of the causes and/or origins of failure in circuits which fail intermittently. Data is acquired in the normal manner on each pass through the test pattern. At the end of each test pattern execution a pass/fail signal from the tester exercising the circuit is used to reject or accept the acquired data. In this fashion, it is possible to accumulate only that data which carries information about the failure of interest and to reject data which does not. Over several test pattern repetitions it is possible to display only that data which shows the failure. Engineers are thus able to efficiently diagnose intermittent failures without the need to change device operating parameters.

Abstract: Apparatus is provided which includes a FIB column having a vacuum chamber for receiving an IC, means for applying a FIB to the IC, means for detecting secondary charged particles emitted as the FIB is applied to the IC, and means for electrically stimulating the IC as the FIB is applied to the IC. The apparatus may be used, for example, (1) to locate a conductor buried under dielectric material within the IC, (2) for determining milling end-point when using the FIB to expose a buried conductor of the IC, and (3) to verify the repair of an IC step-by-step as the repair is made.

Abstract: The present invention provides methods and apparatus for rapid compression of images composed of pixels into high-resolutions, compressed icon images, and for dynamic fault imaging of operating faults in integrated circuit devices employing such methods. Displaying a plurality of such icons juxtaposed on a screen permits ready tracing of a fault in an IC device under test, even by persons having little knowledge of the functionality of the devices.In accordance with the invention, an image made up of n.times.n pixels may be compressed into an icon of p.times.p pixels, where n.dbd.P.multidot.q and q is an integer, by dividing the image into p tiles of q.times.q pixels, selecting q pixels from each tile, where each of said selected q pixels is representative of predetermined directional orientations within the tile, and calculating the mean value of the selected q pixels, to produce a single pixel representative of the tile. The pixels representative of said tiles thus form an icon of p.times.p pixels.

Abstract: Apparatus is disclosed for rapidly computing the Gaussian of Laplacian convolution of the point values in an image. Speed and hardward efficiency are achieved through the use of the separability of higher dimensional Gaussians, the binomial approximation to the one-dimensional Gaussian, the zero mean of Laplacian filtered signals, the reduced sampling requirements for low pass filtered signals, and a binary correlator that does many correlations in parallel, allows correction for geometric distortion and variable sampling density.

Abstract: A method for determining alignment and critical dimensions of regions formed on a semiconductor structure during one or more process steps includes the steps of defining a pattern A at a first location on the semiconductor device during a process step, defining a second independent pattern B at the first location on the semiconductor structure during another process step, acquiring an image of the combination A and B of both the first and second patterns, filtering that image to attenuate higher spatial frequencies while preserving lower spatial frequencies, and comparing the sign result of the filtered image with the sign result of a stored image of the individual patterns to determine alignment errors. In the preferred embodiment the step of filtering includes taking the Laplacian of Gaussian convolution of the image and saving the sign of the result. The comparison between the filtered image and the stored image uses the correlation function for the filtered images.

Abstract: A dual-sided test head for an integrated circuit test system. Each side of the test head has a floating contact surface which provides an electrical contact interface between one side of the test head and a respective load board. Each load board is part of a respective integrated circuit handling system. As the test head has two sides and a load board is contacted at each side, the floating contact surfaces facilitate docking of the test head to the respective load boards. The contactors are floating so as to have freedom of motion to rotate, tilt, offset laterally or offset vertically, relative to the test head.

Abstract: An improved lead for surface-mounted electronic components is described. The improved lead includes an opening through the portion of the lead to be placed in contact with the printed circuit board for soldering. The opening, having a diameter approximately equal to the thickness of the lead, enables the detection of correctly-soldered joints using automated inspection equipment. When the lead is correctly soldered, solder is drawn by capillary action into the opening where it forms a meniscus. By automatically detecting the curvature of the meniscus, the quality of the solder joint may be determined.

Abstract: Methods and apparatus are disclosed for rapid and interactive "warping" of a first image made up of pixels to form a resulting image made up of pixels which are aligned, pixel-for-pixel, with a second image made up of pixels. The images may be stroboscopic voltage contrast images representing operating states of two integrated circuit devices--a failing device and a fully functional device. The aligned images permit an engineer who may have little knowledge of the device to diagnose dynamic failures of the failing device by comparing the aligned images to produce an image showing the differences.

Abstract: A formatter for combining timing signals with data from an algorithmic pattern generator (APG). In the disclosed embodiment, the formatter receives address signals from an APG and timing signals from a timing unit. Each timing signal from the timing unit corresponds to an address signal received from the APG. The address and timing signals are communicated to a signal select unit wherein each timing signal selects its corresponding APG address signal. The selected APG address signal then is communicated to a signal combining unit which combines the APG address with its corresponding timing signal and generates leading edge and trailing edge marker pulses having a user-specified pulse width.

Abstract: A method and apparatus for performing kinematic analysis of linkages is disclosed. Generalized mechanisms are selected from a catalog of mechanisms. From an initial selection of mechanisms, the one most closely matching a desired behavior is chosen and an optimization procedure is conducted. The method may be preceded by a qualitative kinematic analysis or the qualitative analysis may be used in lieu of a catalog selection. An improved optimization technique is disclosed, along with a closed form kinematic analysis method.

Abstract: A computer-aided machining system is described which implements a method of geometrically-intersecting offset surfaces and drive surface to automatically generate tool control paths. Preferably, the machine tool is controlled by characterizing the shape of the part to be milled using the mathematical representation, and from that mathematical representation calculating an approximate offset surface for the surface to be milled. The approximate offset surface is compared with the drive surface for the machine tool to define an approximate tool control point curve. The actual tool control point curve is then calculated by comparing the approximate tool control point curve with the mathematical representation of the surface of the part. The actual tool control point curve can then be supplied to a machine tool to enable it to mill the part surface.

Abstract: A circuit for calibrating linear delay lines wherein a periodic ramp voltage is counted a fixed number of times at first and second frequencies. While the ramp voltages are being counted at each frequency, system clock pulses are counted. The number of system clock pulses counted for each first and second ramp voltage frequency is used to adjust the charging current applied to an integrator which establishes the delay value.

Abstract: A multichannel automatic test system for an electronic circuit utilizes a "true tester-per-pin" architecture; each channel of the tester operates as if it were an independent tester. Each channel of the tester has a memory circuit which stores instructions for operating that channel of the tester. Each of these memories is cycled to the next address to provide a new instruction for that channel, only when it is necessary to change the state of operation of that channel. Thus, the timing of the events on one channel are independent of the timing on the events of any other channel in the tester. The architecture permits the use of dynamic random access memory (DRAM) circuits and allows for backward looping in the test sequence through the use of a cache memory circuit in each channel. The instructions for operating each channel of the tester are context-dependent; that is, the present state of operation of that channel of the tester is utilized in interpreting the next instruction for that channel.

Abstract: A manipulator apparatus for supporting and orienting the test head (11) of an automatic test equipment. A column assembly (14) has a sheath (26) which moves vertically and which is connected via a cable to a manually adjustable counterbalancing device (41) for supporting the weight of the test head (11). A ring (54) is mounted for rotation on the sheath (26) with a side portion (63) slidably receiving an arm (64). A block (81) is mounted for rotation about a vertical axis (theta-z) at the end of arm (64). A frame (90) is mounted in block (81) to rotate about a horizontal axis (theta-x), the test head having a radially extending arm (12) mounted for rotation about an additional axis (theta-y). The a frame (90) contains a circular disk (100) which supports the test head (11), and rollers (97) to support and center the disk. The block (81) and frame (90) are adjustably attached to each other to prevent the head (11) from tilting about horizontal axis (theta-x).

Abstract: A method and apparatus for measuring feature dimensions uses selective dark-field illumination to illuminate a target from a single direction at a low angle to the plane of the target. Opposing edges of the target elements are distinguished and captured in separate images. The images are filtered using a Gaussian convolution operator and a Laplacian operator. The signs of the filtered images are correlated at various offsets. The relative displacement of the images which produces the maxium correlation value is used to calculate the average dimension of the target elements.

Abstract: A process which stores a representation of a polygon forming a portion of a three-dimensional object and compares the polygon to pixels from a scan line as they are passed by. The processor stores a representation of a polygon and compares each pixel passed by the processor to the polygon to determine whether the pixel is within the polygon. If the pixel is within the polygon, its Z position (depth) is compared to the Z position of a corresponding position in the polygon. If the Z position of the polygon position is in front of the Z position of the pixel so that the polygon would obscure the previous pixel description, the Z position and an associates material value (e.g., color) of the polygon is substituted for the Z position of the pixel. The three-dimensional object is preferably represented with triangles and each polygon processor is preferably a triangle processor, with a series of triangle processors arranged in a pipeline. Two pipelines may be provided in parallel.

Abstract: A manipulator apparatus for supporting and orienting the test head (11) of an automatic test equipment. A column assembly (14) has a sheath (26) which moves vertically and which is connected via a cable to a manually adjustable counterbalancing device (41) for supporting the weight of the test head (11). A ring (54) is mounted for rotation on the sheath (26) with a side portion (63) slidably receiving an arm (64). A block (81) is mounted for rotation about a vertical axis (theta-z) at the end of arm (64). Orienting means (16) are mounted in block (81) to rotate about a horizontal axis (theta-x), the test head having a radially extending arm (12) mounted for rotation about an additional axis (theta-y). Adjustment means are disposed between block (81) and orienting means (16) to prevent the head (11) from tilting about horizontal axis (theta-x).

Abstract: A custom bus for a visual signal (image) processing system which can interface with a standard high speed industrial standard computer bus and requires minimal interface circuitry. Eight lines are dedicated to eight data/address bits which are supplied to a bidirectional I/O buffer on each VSP circuit card. A separate board select signal is supplied to each circuit card to enable the I/O buffer. Six bits on six lines provided to each VSP circuit card provide a signal selecting a particular device on each circuit card. Each circuit card contains a decoding circuit for decoding the device select signal and enabling an individual device on the card in response to the device select signal.

Abstract: A multichannel automatic test system for an electronic circuit utilizes a "true tester-per-pin" architecture; each channel of the tester operates as if it were an independent tester. Each channel of the tester has a memory circuit which stores instructions for operating that channel of the tester. Each of these memories is cycled to the next address to provide a new instruction for that channel, only when it is necessary to change the state of operation of that channel. Thus, the timing of the events on one channel are independent of the timing on the events of any other channel in the tester. The architecture permits the use of dynamic random access memory (DRAM) circuits and allows for backward looping in the test sequence through the use of a cache memory circuit in each channel. The instructions for operating each channel of the tester are context-dependent; that is, the present state of operation of that channel of the tester is utilized in interpreting the next instruction for that channel.