Abstract: A charged particle beam system such as a focused ion beam system includes a vacuum chamber; an optical microscope located so as to have a filed of view within a first region of the chamber; a laser aligned with the optical microscope so as to project a laser beam into the first region; a charged particle beam column located within the chamber and arranged so as to focus a charged particle beam into a second region of the chamber; and specimen support located in the chamber and moveable between a first position in the first region and a second position in the second region. The laser is used to mark a DUT with a registration mark which is visible in the images from the optical microscope and the charged particle beam. The position of the registration mark can be accurately determined in the optical image and the position of features which would otherwise be invisible in the charged particle beam image inferred.

Abstract: A test programming architecture provides an application development and execution framework for the development and execution of test programs for a programmable tester for circuits, including a view class library encapsulating objects of a windowing system, one or more tools having view objects for interacting with a user, a visual interface class library framework providing common tool functionality by defining behavior common to tools in a superclass for individual tools, a persistent object environment manager (POEM), an object database accessible to the POEM module for database transactions, and an object request broker providing communication among view objects in tools, test objects in POEM, and a test program running on the tester.

Abstract: An algorithmic pattern generator (APG) having extended register programming capability for use in a circuit tester. The APG is programmable to drive a subroutine memory in a tester. The APG may include a sequencer with paired loop counters, address generators having address and reference registers each paired with indexing registers, a data generator providing bit inversion with a latched inversion register, a topology memory, or a delayed access pipeline for data synchronization. The APG may also include a two stage address scrambler combining a crosspoint multiplexer and scrambler RAM.

Abstract: A focused ion beam is used to etch material from a specimen while directing a vapor of 1,2 di-iodo-ethane at the surface being etched. The etch rate is accelerated for surfaces of aluminum and gold relative to the etch rate without use of 1,2 di-iodo-ethane.

Abstract: Apparatus to provide security for a keypad processor of a transaction terminal includes a secured processor coupled to a keypad and processor of the transaction terminal. The apparatus may operate in a secured or an unsecured mode. In a secured mode, the apparatus prevents the fraudulent acquisition of information, such as personal identification numbers (PIN), entered through the keypad. By encrypting data entered through the keypad, the apparatus prevents the fraudulent acquisition of information transmitted to a processor such as a central computer of a bank. The secured processor provides actual and false sampling of the keypad and simulates keypad data entries to prevent an electronic eavesdropper from determining the actual keypad entries.

Abstract: Methods are provided for exposing a selected feature of an IC device, such as a selected conductor, from the back side of the substrate without disturbing adjacent features of the device, such as active regions. One such method comprises: (a) determining a region of the IC device in which the selected feature is located; (b) acquiring from the back side of the substrate an IR optical microscope image of the region; (c) aligning the IR optical microscope image with a coordinate system of a milling system; and (d) using structures visible in the IR optical microscope image as a guide, operating the milling system to expose the selected feature from the back side of the IC device without disturbing adjacent features.

Abstract: Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT.

Abstract: Apparatus for supplying a jet of chemical vapor at a substantially constant rate comprises a crucible for containing a quantity of chemical, a hollow needle, a flow path from the crucible to the hollow needle, a Peltier element in thermal communication with the crucible, and a temperature control circuit responsive to temperature in the crucible for powering the Peltier element so as to maintain temperature of the crucible substantially constant. The temperature control circuit powers the Peltier element so as to maintain temperature of the crucible below (or above) ambient temperature. The apparatus is useful in a system for modifying an integrated circuit specimen which further comprises a vacuum chamber and an ion-optical column for directing a focused ion beam at an integrated circuit specimen within the vacuum chamber. Control of vapor pressure, and thus flow rate, offers improved control over FIB processing of integrated circuit specimens.

Abstract: A multi-level driver circuit comprises: (a) an output buffer; (b) a first switch for applying a first analog level to the output buffer when in a closed state; (c) a second switch for applying a second analog level to the output buffer when in a closed state; (d) a third switch for applying a third analog level to the output buffer when in a closed state, wherein the third switch applies to the output buffer a capacitance which is dependent upon level when the third switch is in an open state and is unclamped; and (e) a clamping circuit for clamping the third switch such that the third switch applies to the output buffer a capacitance which is substantially independent of the third analog level when the third switch is in an open state and is clamped by the clamping circuit. The switches can be solid-state switches, such as diode bridges. Any number of switches can be provided, and more than one of the switches can be provided with a clamping circuit.

Abstract: Waveforms are acquired from a DUT into segments corresponding respectively to vectors of a vector pattern repetitively applied to the DUT. The waveform segments are displayed relative to vector numbers of the pattern to facilitate comparison of stimulus/response, debug, and other tasks. The relationship of the vector pattern is known relative to a trigger occurring once per repetition of the pattern, and vectors of the pattern are synchronous with a vector clock. The relationship of the time-domain waveform to the trigger is known. Taking account of these relationships and of system delays, each acquired waveform segment can be associated as it is acquired with a start-of-vector mark and with the corresponding vector number. Waveform displays are prepared which show the waveform segments corresponding to vector numbers of a user-selected range of vectors.

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal.

Abstract: Methods are provided for depositing insulator material at a pre-defined area of an integrated circuit (IC) by: placing an IC in a vacuum chamber; applying to a localized surface region of the integrated circuit at which insulator material is to be deposited a first gas containing molecules of a dissociable compound comprising atoms of silicon and oxygen and a second gas containing molecules of a compound which reacts with metal ions; generating a focused ion beam having metal ions of sufficient energy to dissociate molecules of the first gas; and directing the focused ion beam at the localized surface region to dissociate at least some of the molecules of the first gas and to thereby deposit on at least a portion of the localized surface region a material containing atoms of silicon and oxygen. The dissociable compound comprises atoms of carbon and hydrogen, such as di-t-butoxydiacetoxy-silane. The compound which reacts with metal ions may be carbon tetrabromide or ammonium carbonate.

Abstract: Probe-point placement methods are described. A layout description, a netlist description and a cross-reference description of an IC are retrieved from storage. The data structures associate with each net name a list of polygons. Polygons of a selected net are broken into segments of a specified step size. Each segment is evaluated in accordance with a set of prober rules. Values produced by the prober rules are weighted and combined to obtain a prober score for each segment. The prober score indicates suitability of the corresponding net location for probing. If the best prober score indicates an optimal segment exists for probing, the coordinates of that segment are stored and used to direct a probe to the corresponding location of the IC. If the best prober score indicates no optimal segment exists for probing, each segment of the net is evaluated in accordance with a set of probe-point cutter rules.

Abstract: A test system, for testing circuits, having two operating modes, a normal mode and an accelerated mode. The test system has a first start memory, a second start memory, a first sequence memory, and a second sequence memory. The start memories provide sequence memory addresses for addressing the sequence memories, and the sequence memories provide event sequences in response to sequence memory addresses. If operating in normal mode, the start memories are electronically coupled (switched) to provide a single sequence memory address to both sequence memories. If operating in accelerated mode, the start memories are electronically coupled so that the first start memory provides a first sequence memory address to the first sequence memory and the second start memory provides an independent second sequence memory address to the second sequence memory.

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal.

Abstract: Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT.

Abstract: A tester exercises a DUT with a repetitive signal pattern, supplying a trigger signal for each repetition. The waveform on a conductor of the DUT is to be acquired by repeatedly measuring voltage at each of a number of sample points following the trigger, using a charged-particle probe system having an integrator-filter loop for analyzing energy of secondary particles. Before measurement at a sample point, integrator is reset and the filter voltage needed to settle the loop for the sample point is set using a predictive scheme. When the measurement is made, the predicted filter voltage is summed with the integrator output voltage to produce the actual filter voltage. The integrator then measures the error between the predicted filter voltage and the actual filter voltage needed to settle the loop. The time needed to settle the loop is thereby minimized. Various predictive schemes can be used.

Abstract: Preferential etching during FIB milling can result in a rough, pitted surface and make IC probing/repair operations difficult. Preferential etching is compensated by acquiring a contrast image of the partially-milled sample, preparing mask image data from the contrast image, and controlling further FIB milling using the mask image data. For example, a window is to be milled in a top-layer power plane of an IC to expose a hidden layer. The window is partially milled. A FIB image is acquired and thresholded to produce mask image data. The mask image data distinguish areas where the power plane has been milled through from those where it has not been milled through. Milling is resumed using the mask image data to control effective FIB milling current. The mask image data are updated periodically as the window is milled.

Abstract: Offset between a pair of images is determined using parallel processing techniques in a general-purpose digital serial processor. For each each image, a patch of pixels is selected and convolved with a Laplacian kernel. The result is convolved with a Gaussian kernel in each of the x- and y-directions to produce a registration image. The registration images are binarized, bit-packed, and correlated to one another by performing an EXOR operation for each pixel location at each of a plurality of relative offsets of the images. The results of the EXOR operation are summed to produce an image-correlation value for each relative offset. The image-correlation indicating highest correlation determines relative offset of the images. The determined offset can be used for a variety of purposes in automating control of E-beam and FIB systems, to register images to one another or to identify a location in one image which corresponds to a selected location of the other image.

Abstract: Probe-point placement methods are described. A layout description, a netlist description and a cross-reference description of an IC are retrieved from storage. The data structures associate with each net name a list of polygons. Polygons of a selected net are broken into segments of a specified step size. Each segment is evaluated in accordance with a set of prober rules. Values produced by the prober rules are weighted and combined to obtain a prober score for each segment. The prober score indicates suitability of the corresponding net location for probing. If the best prober score indicates an optimal segment exists for probing, the coordinates of that segment are stored and used to direct a probe to the corresponding location of the IC. If the best prober score indicates no optimal segment exists for probing, each segment of the net is evaluated in accordance with a set of probe-point cutter rules.