Abstract: A circuit for generating successive points on a sine wave using the Coordinate Rotational Digital Computer (CORDIC) algorithm. An angle memory and an amplitude memory store respective angle and amplitude values from which a CORDIC logic processor calculates a point on a sine wave. A frequency memory stores an increment value unique to the frequency of the sine wave to be formed, and an arithmetic logic unit adds the increment value to the stored angle value after the point on the sine wave is calculated. The CORDIC logic processor then calculates the next point on the sine wave from the incremented angle value. A digital-to-analog converter may be used to provide an analog output signal.For generating multi-tone signals, the angle, amplitude and frequency memories are configured to store a plurality of angle, amplitude and increment values, and an address memory is connected to each memory for simultaneously addressing them.

Abstract: A system is provided for application of a lighting model to a rasterized stream of pixels. The system typically includes a series of circuits, each for applying a lighting model to a single pixel. Each chip typically includes some memory sources for storing the lighting model, an input section connected to receive data indicative of the normal vector, Z depth, and material characteristics of the object represented by the pixel to be colored. A special purpose processor connected to the input then applies the lighting model to the pixel and supplies color value of the pixel as an output signal.

Abstract: A method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating addresses corresponding to addresses for the source image with one or more of the most significant bits modified so that the address sequence received by the second and subsequent memories are identical to the address sequence received by the first memory. This allows the various blocks of the image in the different memories to be later simulataneously accessed in parallel using a single address sequence.

Abstract: A system for in-circuit testing of an electronic circuit device utilizes a distributed processing architecture wherein separate controllers are used to control the testing and for data collection and correlation of the collected data to the testing conditons. In a preferred embodiment, the testing is conducted by sending test vector addresses from the test controller to each of the driver/sensor boards in the testor electronics, which addresses, in turn, are used to access driver memories containing the test conditions corresponding to the test vector addresses. In the method of the present invention, the circuit containing the device is powered up and a tester coupling mechanism is connected to the terminals of the device. Determinations are made of the physical orientation of the device with respect to the tester coupling mechanism, and of whether the device terminals are in electrical contact with the tester mechanism and with the other components of the circuit.

Abstract: A network of filter elements for transforming an analog signal of infinite bandwidth into a discrete filter space representation having a bandwidth equal to .pi.. In one embodiment the filter network includes Laguerre filter elements. Other embodiments include methods for estimating the values of the amplitudes, frequencies, and phases of the frequency components of the analog signal, for reconstructing an input signal, and correcting for non-ideal filter elements.