Patents Assigned to Scintera Networks, Inc.
  • Publication number: 20070064845
    Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
    Type: Application
    Filed: October 26, 2006
    Publication date: March 22, 2007
    Applicant: SCINTERA NETWORKS, INC.
    Inventors: Abhijit Phanse, Abhijit Shanbhag
  • Patent number: 7170274
    Abstract: A bandgap reference includes a current source providing a current that is proportional to the sum of a first voltage having a positive-to-absolute-temperature (PTAT) temperature dependency and a second voltage having a complementary-to-absolute-temperature (CTAT) dependency. The bandgap reference further includes a variable resistor comprising a fixed resistor that may be selectively combined with one or more of a plurality of selectable resistors, wherein the first voltage is inversely proportional to the resistance of the variable resistor.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: January 30, 2007
    Assignee: Scintera Networks, Inc.
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Abhijit Phanse
  • Patent number: 7170349
    Abstract: T-coil structures are used in one embodiment to inject programmably-variable amounts of transistor biasing currents into the respective drains of current sinking transistor means of a broadband differential amplifier such that, when the differential amplifier is in common mode, total transistor drain current will exceed total voltage-dropping current passing through corresponding voltage-dropping resistances of the amplifier's transistor means. The T-coil structures keep the parasitic capacitances of the programmable current sources that provide the bias currents de-lumped from capacitances of the amplifier's output nodes and/or capacitances of the amplifier's voltage-dropping resistances (variable resistances) to thereby maintain a wide bandwidth.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: January 30, 2007
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee
  • Patent number: 7130366
    Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: October 31, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit Phanse, Abhijit G. Shanbhag
  • Patent number: 7120193
    Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: October 10, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Edem Ibragimov, Qian Yu, Prashant Choudhary
  • Patent number: 7078969
    Abstract: A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0?r?1 and such that a second input voltage may be multiplied by the complement factor (1?r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 18, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Patent number: 7061978
    Abstract: In accordance with the presently claimed invention, compensation for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: June 13, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 7053688
    Abstract: A low-voltage constrained coefficient adaptation and multiplication is provided. To provide the constrained coefficient adaptation, an adder adds an adaptive differential control voltage to a forcing differential control voltage to provide an effective coefficient. The adder is configured such that the forcing differential control voltage can prevent the adaptive differential control voltage from producing a sign change in the effective coefficient.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: May 30, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Abhijit Phanse
  • Publication number: 20060104342
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Application
    Filed: November 21, 2005
    Publication date: May 18, 2006
    Applicant: Scintera Networks, Inc.
    Inventors: Abhijit Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian
  • Patent number: 7039104
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 2, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian
  • Patent number: 7035330
    Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit M. Phanse, Jishnu Bhatacharjee, Debanjan Mukherjee, Venugopal Balasubramonian, Fabian Giroud, Edem Ibragimov
  • Patent number: 7031383
    Abstract: A compensation circuit for reducing intersymbol interference (ISI) products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium provides for selective application of compensation to individual, discrete data signal components. According to one embodiment, one circuit branch processes the electrical data signal to substantially remove one distinct signal component representing an ISI product of some portion of the data symbol sequence. A second circuit branch approximately duplicates an ISI product of another portion of the data symbol sequence for removal by subtraction within a signal combiner from the compensated signal provided by the first circuit branch. A third circuit branch approximately duplicates an ISI product of still another portion of the data symbol sequence also for removal by subtraction within the signal combiner from the compensated signal provided by the first circuit branch.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: April 18, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 7020402
    Abstract: A crosstalk compensation engine for reducing signal crosstalk effects within a data signal. Demultiplexed data signals corresponding to multiplexed data signals received via a signal transmission medium are processed to significantly reduce one or more signal crosstalk products related to one or more interactions among the multiplexed data signals within the signal transmission medium. Such signal crosstalk products include those resulting from dense wavelength-division mutiplexing of the data signals used to provide the multiplexed data signals, four-wave mixing among the multiplexed data signals within the signal transmission medium, and cross-phase modulation among the multiplexed data signals within the signal transmission medium.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: March 28, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 6985036
    Abstract: A digitally controlled transconductance cell includes a differential transistor pair coupled to load elements (either passive or active with resistive or impedance loads) and a variable bias current source, where the transconductance or gain is digitally varied by changing the aspect ratio of the transistors and the bias current.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: January 10, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Publication number: 20050271138
    Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
    Type: Application
    Filed: July 21, 2005
    Publication date: December 8, 2005
    Applicant: Scintera Networks, Inc.
    Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Edem Ibragimov, Fabian Giroud
  • Patent number: 6965337
    Abstract: Systems and methods are disclosed herein to provide reference generators. For example, in accordance with an embodiment of the present invention, a reference generator is provided for an electrical device, such as for example for an analog-to-digital converter. The reference generator may provide one or more reference signals having a common mode voltage that can track or be varied based on a common mode voltage of an input signal. Alternatively or in addition, the reference generator may provide reference signals for single-ended applications.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: November 15, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud
  • Patent number: 6952132
    Abstract: Systems and methods provide automatic gain control, such as by employing analog and digital techniques. For example, overall gain may be controlled through coarse and fine control signals provided to gain stages, with the overall gain monitored via a power detector circuit.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: October 4, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Patent number: 6940352
    Abstract: A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0?r?1 and such that a second input voltage may be multiplied by the complement factor (1?r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 6, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Patent number: 6940386
    Abstract: An integrated circuit including a differentially excited symmetric microstrip inductor formed over multiple layers while maintaining both electrical and geometrical symmetry.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 6, 2005
    Assignee: Scintera Networks, Inc
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Abhijit Phanse
  • Patent number: 6940898
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 6, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian