Abstract: The technology disclosed herein provides a method including determining an acceptable parameter rate for a dual reader storage device having dual readers, identifying one of the dual readers as the preferable reader, comparing an actual parameter rate of the storage device to the acceptable parameter rate of the storage device, and in response to determining that the actual parameter rate is below the acceptable parameter rate, operating the storage device using only the preferable reader. In one implementation, the parameter rate is bit-error rate (BER) of the dual readers.
Abstract: A magnetic recording head includes a write pole including an end proximal to a media-facing surface of the magnetic recording head, a return pole disposed a distance from the write pole in a down-track dimension of the magnetic recording head, and a writer coil configured to produce a magnetic flux in the write pole. The writer coil includes a first segment and a second segment. The first segment is disposed proximal to the end of the write pole and between the write pole and the return pole. The second segment is electrically coupled to the first segment. A thickness of the second segment in the down-track dimension is greater than a thickness of the first segment in the down-track dimension.
Abstract: A heat-assisted magnetic recording (HAMR) device is configured to write regions of neutral polarity on a magnetic media during a same pass of the recording head in which other regions are written of positive polarity and negative polarity. The various disclosed write techniques may facilitate creation of “zero state” (substantially net zero polarity) transition zones between each pair of data bits of opposite polarity and/or may facilitate the encoding of three different logical states (e.g., 1, 0, and ?1) on the media.
Type:
Grant
Filed:
December 29, 2021
Date of Patent:
April 11, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Thomas Young Chang, Philip L. Steiner, Zengyuan Liu
Abstract: A heat-assisted magnetic recording (HAMR) device is configured to write regions of neutral polarity on a magnetic media during a same pass of the recording head in which other regions are written of positive polarity and negative polarity. The various disclosed write techniques may facilitate creation of “zero state” (substantially net zero polarity) transition zones between each pair of data bits of opposite polarity and/or may facilitate the encoding of three different logical states (e.g., 1, 0, and ?1) on the media.
Type:
Grant
Filed:
December 29, 2021
Date of Patent:
April 11, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Thomas Young Chang, Philip L. Steiner, Zengyuan Liu
Abstract: A method includes importing an object into a first data storage device, obtaining static metadata relating to the object, and obtaining dynamic metadata relating to the importation of the object. The static metadata and the dynamic metadata are hashed to create a block hash for the object and the importation of the object. The imported object and the block hash are stored in the first data storage device.
Type:
Grant
Filed:
September 3, 2020
Date of Patent:
April 4, 2023
Assignee:
Seagate Technology LLC
Inventors:
Dieter P. Schnabel, Francois Xavier Hannedouche, Nicholas James Dance, Ujjwal Lanjewar, John Anthony Fletcher
Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.
Type:
Grant
Filed:
April 19, 2022
Date of Patent:
March 28, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Shuhei Tanakamaru, Dana Lynn Simonson, Erich Franz Haratsch
Abstract: Systems and methods are disclosed for data storage redeployment. For example, a controller of a data storage array can implement a process to determine when, or if, to redeploy a data storage device from a first data storage usage or tier having a first performance requirement to a second data storage usage or tier having a second performance requirement. In some embodiments, the first data storage tier performance requirement is for hot-data storage, and the second data storage tier performance requirement is for cold-data storage. Various criterion (e.g., a data storage device performance metric) threshold, such as a workload (e.g., LBAs written, LBAs read, or both) of the data storage device or bit error rate (BER), may be utilized in a redeployment determination.
Abstract: A data storage system can consist of a network controller connected to a data storage device and a remote host. An attack mitigation strategy may be generated with an attack module connected to the network controller in response to detected data storage conditions in the data storage device. The attack mitigation strategy can be executed with the attack module by sending separate first and second security queries to the data storage device over time. At least a powered move attack can then be identified based on the second security query.
Type:
Grant
Filed:
June 5, 2020
Date of Patent:
March 21, 2023
Assignee:
Seagate Technology LLC
Inventors:
Christopher N. Allo, Saheb Biswas, Kevin G. Sternberg
Abstract: A data storage device can have one or more rotating data media with data tracks that are radially disposed from a central spindle. The data tracks may be logically divided into multiple regions while a write strategy is generated with a region module to set a sequence of different regions for future data writes. Receipt of a data write request to the data storage media from a host can prompt the region module to classify the data write request as a sequential or random write in order to intelligently select a region to satisfy the data write request based on the write strategy to maximize data writing consistency for data associated with the data write request.
Abstract: Cache coherency of a global address space of a cache can be maintained with one or more tier control units (TCUs). The global address space of the cache may be shared by multiple domains. Domains may include multiple controllers and a local interconnect operatively coupling the controllers to the cache. The local interconnect of each domain may maintain a cache coherency of a local address space of the cache shared by the controllers of the domain. The one or more TCUs may be operatively coupled to the local interconnects of the domains to maintain the cache coherency of the global address space.
Abstract: Features are detected from a sensor signal via a deep-learning network or other feature engineering methods in an edge processing node. Machine-learned metadata is created that describes the features, and a hash is created with the machine-learned metadata. The sensor signal is stored as a content object at the edge processing node, the object being keyed with the hash at, the edge processing node.
Type:
Grant
Filed:
October 10, 2019
Date of Patent:
March 7, 2023
Assignee:
Seagate Technology LLC
Inventors:
Lijuan Zhong, Krishnan Subramanian, Mehmet Fatih Erden, Jon D. Trantham
Abstract: A computation is divided into computation tasks that are sent to worker nodes and distributed results are received in response. A redundant subtask is sent to each of the worker nodes, the redundant subtask being a random linear combination of the computation tasks sent to others of the worker nodes. The worker nodes perform the redundant subtasks to produce redundant results. The redundant result of each worker node is combined with distributed results of others of the worker nodes to determine whether one or more of the worker nodes are acting maliciously. Optionally, the worker nodes can be initially evaluated for trustworthiness using a homomorphic hash function applied to an initial computation task and applied to results of the initial tasks. If the results of both hash functions match, then the worker nodes are considered trustworthy and can be used for subsequent computations with redundant subtasks as described above.
Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.
Type:
Grant
Filed:
April 29, 2022
Date of Patent:
February 28, 2023
Assignee:
Seagate Technology LLC
Inventors:
Naveen Kumar, Shuhei Tanakamaru, Erich Franz Haratsch
Abstract: A machine learning system and method. The machine learning system includes at least one computation circuit that performs a weighted summation of incoming signals and provides a resulting signal. The weighted summation is carried out at least in part by a magnetic element in which weights are adjusted based on changes in effective magnetic susceptibility of the magnetic element.
Type:
Grant
Filed:
January 3, 2019
Date of Patent:
February 28, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Kirill A. Rivkin, Javier Guzman, Mourad Benakli
Abstract: Method of utilizing a nanochannel in combination with at least one magnetic sensor for detecting (e.g., identifying) molecules, cells, and other analytes. Particularly, the method includes bringing molecules, labeled with magnetic nanoparticles (MNPs), in close proximity to the magnetic sensor to identify the molecules via an output signal from the magnetic sensor. The method is particularly suited for identifying nucleotides of DNA and RNA strands.
Type:
Grant
Filed:
October 2, 2019
Date of Patent:
February 28, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Gemma Mendonsa, Riyan A. Mendonsa, Krishnan Subramanian
Abstract: Systems and methods are disclosed for the intelligent scheduling of garbage collection operations on a solid state memory. In certain embodiments, a method may comprise initiating a garbage collection process for a solid state memory (SSM) having a multiple die architecture, determining an order of die access for the garbage collection process based on an activity table indicating a use of one or more die in the multiple die architecture, and performing the garbage collection process based on the determined order of die access. Garbage collection reads may be directed to idle die to avoid conflicts with die busy performing other operations, thereby improving system performance.
Abstract: A method includes receiving at a storage device a command from a host. When learning is active on the storage device, an initial parameter value of a plurality of parameter values is used for performing a first action of a plurality of actions for the command. The first action is performed using the initial parameter value of the plurality of parameter values for the command The first parameter value is incremented to a next parameter value of the plurality of parameter values for the command for use in reperforming the first action.
Type:
Grant
Filed:
September 11, 2020
Date of Patent:
February 28, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Harry Tiotantra, Jun Cai, Kai Chen, WeiQing Zhou, Feng Shen
Abstract: Systems and methods are disclosed for detecting shingled overwrite errors. When a read error is encountered when reading from shingled recording tracks, a processor may determine whether the read error is an error caused by shingled overwriting. The processor may determine whether the read error is caused by shingled overwriting by determining read signal quality of one or more sectors preceding the read error, such as based on a bit error count or bit error ratio (BER), and comparing the read signal quality to a threshold value. The processor may determine that the read error is caused by shingled overwriting when the read signal quality value is lower than the threshold.
Type:
Grant
Filed:
December 19, 2016
Date of Patent:
February 28, 2023
Assignee:
Seagate Technology LLC
Inventors:
Xiong Liu, WeiQing Zhou, Quan Li, WenXiang Xie
Abstract: Systems and processes are disclosed to preserve data integrity during a storage controller failure. In some examples, a storage controller of an active-active controller configuration can back-up data and corresponding cache elements to allow a surviving controller to construct a correct state of a failed controller's write cache. To accomplish this, the systems and processes can implement a relative time stamp for the cache elements that allow the backed-up data to be merged on a block-by-block basis.
Type:
Grant
Filed:
May 4, 2022
Date of Patent:
February 28, 2023
Assignee:
Seagate Technology LLC
Inventors:
Adithya Uligere Narasimhamurthy, Ritvik Viswanatha, Michael Barrell
Abstract: Apparatus and method for local authentication of a collection of processing devices, such as but not limited to storage devices (e.g., SSDs, etc.). In some embodiments, an edge computing device is coupled between the collection of processing devices and an external network. The edge computing device performs a network authentication over the external network with a remote server using an edge token. The edge computing device further performs a local authentication of the collection using storage tokens of the respective processing devices, with the local authentication not utilizing the external network or the remote server. Both the edge token and the storage tokens may be generated from a client token of a client device.