Abstract: A virtual solid state storage system is provided with solid state storage error emulation. An exemplary apparatus comprises a virtual solid state storage device configured to emulate a solid state storage device. The virtual solid state storage device comprises an interface that communicates with a solid state storage controller; an address translation module that translates memory addresses from a solid state storage-based memory space to a second memory space of a second memory device; and a non-solid state storage memory controller that communicates with the second memory device; and an error module to emulate solid state storage errors for testing error handling functions of the solid state storage controller for predefined error types of the solid state storage memory device by: (i) flipping bits sent to and/or read from the second memory device; and/or (ii) changing a status response sent to the solid state storage controller.

Abstract: A mobile data storage device (102) may be housed in a mobile computing device (142) without an active cooling feature. The mobile data storage device (102) can have at least a controller (122) configured to delay command execution in response to a predicted mobile data storage device (102) temperature. The controller (122) can insert a plurality of delays into a command queue to prevent the mobile data storage device (102) from reaching the predicted mobile data storage device (102) temperature.

Abstract: A reader having a sensor stack and a top shield above the sensor stack. The top shield has an upper surface and a lower surface. The reader also includes at least one side shield below the top shield and adjacent to the sensor stack. The reader further includes a decoupling layer between the upper surface of the top shield and the at least one side shield. The decoupling layer is configured to decouple a first portion of the at least one side shield, proximate to the sensor stack, from at least a portion of the top shield.

Abstract: An apparatus comprises a slider configured to facilitate heat assisted magnetic recording. The slider comprises a plurality of bond pads including a first electrical bond pad, a second electrical bond pad, and a ground pad. A laser diode comprises an anode coupled to the first electrical bond pad and a cathode coupled to the second electrical bond pad. The laser diode is operable in a non-lasing state and a lasing state. A heater is coupled between the ground pad and at least one of the anode and cathode of the laser diode. The heater is configured to generate heat for heating the laser diode during the non-lasing state and the lasing state.

Abstract: Provided herein is a method that includes receiving a signal to erase content stored on a storage device. The method further includes erasing the content stored on the storage device in response to the signal to erase. The method also includes issuing a certificate of erasure, wherein the certificate is unique to the storage device.

Abstract: Systems and methods for improving data mining systems are described. In one embodiment, the systems and methods may include a storage drive and a hardware controller. In some embodiments, the hardware controller may be configured to detect a first event in the storage system, identify data associated with the first event, parse the data according to a logging protocol, and store the parsed data in a database.

Abstract: Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

Abstract: Methods, systems, and computer-readable storage media for a storage device to, upon receiving a command from a computing host, determine whether or not the command includes location information targeting a particular portion of a NVM of the storage device, the location information having been retrieved by the computing host from a shadow map and included with the command. Upon determining that the command includes location information, the command is processed by the storage device using the included location information. Upon determining that the command does not include location information, the storage device determines the particular portion of the NVM targeted by the command based on a map stored in a memory of the storage device before processing the command.

Abstract: A system utilizing elastic spares includes nodes and devices to store one or more data objects having information. The data object includes data object units each assigned to a storage location on a different node than the other units. The data object includes one or more spare units to store reconstructed information of a failed unit. When one of the data objects has a failed unit and no spare units available to store reconstructed information, a controller of the system assigns an elastic spare unit to an available storage location of one of the nodes. Reconstructed information of the failed unit is stored in the elastic spare unit.

Abstract: Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.

Abstract: A data storage device can employ a front end bus to optimize data storage performance. A first controller may be connected to a first memory via a first bus and to a second memory via a second bus with the first bus and first memory housed within an internal cavity of an enclosure while the second bus is exposed to an exterior surface of the housing and the second memory is separated from the internal cavity. The first controller can be configured to substitute the second memory for the first memory in response to a front end controller identifying a type of data storage of the second memory.

Abstract: A memristor may include an exchange-coupled composite (ECC) portion to provide three or more nonvolatile magneto-resistive states. The ECC portion may include a continuous layer and a granular layer magnetically exchange coupled to the continuous layer. A plurality of memristors may be used in a system to, for example, define a neural network.

Abstract: In a data storage system, latency optimization can be practiced by logging a plurality of data accesses to a memory in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory. The register may be analyzed with a system module to predict a command execution latency value for the plurality of data accesses that can be used to generate a deterministic data access sequence with the system module. A queue of data accesses can then be reorganized from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.

Abstract: An apparatus and system that includes a plurality of data devices, a network module, and a chassis. The network module may include an interface defining couplings and channels extending between the couplings defining a network topology for interconnecting data devices. The chassis may be configured to receive data devices and the network module to operably couple the received data devices via the interconnect topology defined by the network module.

Abstract: Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.

Abstract: Methods, systems, and machine-readable storage medium for multi- tier data recovery utilizing a series of progressively more complex detection and decoding modes based on data from additional pages or wordlines. In one aspect, read data is obtained from at least one cell comprising a given page of a flash memory, and reliability values are generated for the cell from the read data. The reliability values are utilized to decode the read data for the given page. If the decoding of the read data fails, a series of successive decoding steps is performed, with each successive decoding step utilizing additional read data to generate reliability values for the decoding. In one example, reads of one or more additional pages in the same wordline are performed. In a second example, several read retries (soft reads) of the same wordline are performed. In a third example, one or more additional neighboring wordlines are read.

Abstract: Systems and methods are disclosed for die access order variation to a memory having a multiple-die architecture. In certain embodiments, an apparatus may comprise a controller configured to assign a unique die access order to each set of multiple sets of related commands, a die access order controlling an order in which a plurality of dies of a solid state memory are accessed to perform the related commands. A first stream may be assigned a first die access order, and a second stream may be assigned a second, different die access order, thereby distributing the timing of die access collisions between the streams.

Abstract: A method for transferring components from a transfer head to a receiving substrate is disclosed. The method includes monitoring signals indicative of a pitch mismatch between locations on the transfer head and locations on the receiving substrate and actuating at least one actuator based at least in part on the monitored signals to reduce the mismatch of the pitch of the locations on the transfer head and the locations on the receiving substrate.