Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.
Type:
Grant
Filed:
December 9, 2015
Date of Patent:
February 28, 2017
Assignee:
Seagate Technology LLC
Inventors:
AbdelHakim S. Alhussien, Erich F. Haratsch, Earl T. Cohen, Yunxiang Wu
Abstract: The present disclosure relates to feature activation using near field communication. In an embodiment, a device may include a chip to receive and store wireless communications. An activation package may be stored to the chip, and identify a set of features to enable or disable on the device. The device may include a processor to detect the activation package and initiate device operations based on the identified set of features. In some embodiments, the chip may receive and store information while the device is in a powered-off state, and the processor may detect the activation package at a power on event.
Type:
Grant
Filed:
April 4, 2014
Date of Patent:
February 28, 2017
Assignee:
Seagate Technology LLC
Inventors:
Monty A. Forehand, Christopher J DeMattio, Manuel A Offenberg
Abstract: Storage address space to NVM address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping function to convert a logical block address from a host to an address of a smallest read unit of the NVM. The mapping function provides span and length information corresponding to the logical block address. The span information specifies a number of contiguous smallest read units to read to provide data (corresponding to the logical block address) to the host. The length information specifies how much of the contiguous smallest read units relate to the data provided to the host. The converted address and the length information are usable to improve recycling of no longer needed (e.g. released) portions of the NVM, and usable to facilitate recovery from outages and/or unintended interruptions of service.
Abstract: A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.
Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.
Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile memory cells are each programmed to an associated programmed state responsive to a respective amount of accumulated charge. A charge loss compensation circuit adds a relatively small amount of additional charge to the respective amount of accumulated charge in each of the memory cells to maintain the associated programmed states of the cells.
Type:
Grant
Filed:
March 31, 2015
Date of Patent:
February 21, 2017
Assignee:
Seagate Technology LLC
Inventors:
Wei Wang, Antoine Khoueir, Young Pil Kim
Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. An example data processing system includes a first circuit operable to yield a modified soft data set from a data set accessed from a solid state memory device, and a second circuit operable to apply a data decoding algorithm to the modified soft data to yield a decoded output.
Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
Abstract: A storage controller is provided. The storage controller includes a memory storing an indication of a current owner, a previous owner, and a preferred owner for each of one or more logical volumes. The storage controller is configured to write protect the logical volumes where the current owner and the preferred owner is the storage controller and the previous owner of the logical volumes was a different storage controller. For the logical volumes where the storage controller is the preferred but not the current owner, the storage controller is set as the current and preferred owner of the logical volumes that the different storage controller was the current but not the preferred owner for, storage controller is set as the previous owner of the logical volumes that the storage controller is the current and preferred owner of, and allowing read and write access to the one or more logical volumes.
Abstract: Method and apparatus for managing a data storage system that utilizes heat assisted magnetic recording (HAMR). In some embodiments, the method includes recording data to a storage medium using the HAMR system, accumulating a usage statistic indicative of actual elapsed operation of the HAMR system, and setting an indication value in a memory indicative of an estimate of remaining available elapsed operation of the HAMR system. The estimate of remaining available elapsed operation is determined in relation to the usage statistic and an estimated total elapsed operation value.
Type:
Grant
Filed:
November 25, 2015
Date of Patent:
February 14, 2017
Assignee:
Seagate Technology LLC
Inventors:
Tim Rausch, Douglas Murphy, John W. Dykes, Jason Zimmerman, James C. Hatfield
Abstract: Non-volatile memory program failure recovery via redundant arrays enables higher programming bandwidth and/or reduced latency in some storage subsystem implementations, e.g. a solid-state disk. Data to program N portions of a plurality of non-volatile memories is received at a non-volatile memory controller. The data includes particular data to program a particular one of the N portions. The particular data is stored in an allocated buffer associated with the non-volatile memory controller. Programming the particular data to a particular one of the non-volatile memories is begun. Redundancy information sufficient to recover from failures of M of the N portions is updated. The allocated buffer is freed. At least one of the storing, the beginning programming, the updating, and the freeing is in response to the receiving of the particular data. The freeing is prior to the particular non-volatile memory completing the programming.
Type:
Grant
Filed:
December 27, 2012
Date of Patent:
February 14, 2017
Assignee:
Seagate Technology LLC
Inventors:
Jeremy Isaac Nathaniel Werner, Earl T. Cohen
Abstract: A method of forming a near field transducer (NFT), the method including the steps of depositing a plasmonic material; depositing an encapsulant material on at least a portion of the plasmonic material; and implanting ions into at least a portion of the plasmonic material through the encapsulant material.
Abstract: A device having an air bearing surface and a method of forming the device are disclosed. The device can include a writer portion including a surface at the air bearing surface of the device, a magnetic adhesion layer disposed proximate at least a portion of the surface of the writer portion, and an overcoat disposed proximate at least a portion of the magnetic adhesion layer such that the magnetic adhesion layer is between the at least a portion of the surface of the writer portion and the overcoat.
Abstract: Apparatus and method for generating random numbers. In accordance with some embodiments, a first multi-bit string of entropy values is derived from a first entropy source having a first trust level and a different, second multi-bit string of entropy values is derived from a second entropy source having a different, second trust level. The first and second multi-bit strings of entropy values are combined in relation to the associated first and second trust levels to generate a multi-bit random number. The multi-bit random number is used as an input to a cryptographic function.
Type:
Grant
Filed:
October 30, 2014
Date of Patent:
February 14, 2017
Assignee:
Seagate Technology LLC
Inventors:
Sumanth Jannyavula Venkata, Manuel A. Offenberg, William Erik Anderson
Abstract: Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.
Abstract: A method includes performing a first seek operation using a first voice coil motor (VCM) control signal by utilizing a first drag component value. The method further includes determining a position error signal (PES) and a DC offset component of the PES measured during the first seek operation, and determining that the DC offset component is above a predetermined threshold. In response to determining that the DC offset component is above the predetermined threshold, the method further includes determining a second drag component value different than the first drag component value. The method further includes generating a second VCM control signal by applying the second drag component value.
Type:
Grant
Filed:
May 12, 2016
Date of Patent:
February 7, 2017
Assignee:
Seagate Technology LLC
Inventors:
Amar Nath, Ming Zhong Ding, Guo Quing Zhang, Chan Fan Lau
Abstract: Methods and apparatus are provided for read retry operations with read reference voltages ranked for different page populations of a memory. One method comprises obtaining a plurality of rankings of a plurality of read reference voltages for a plurality of page populations, wherein the rankings are based on a predefined performance metric; and reading a codeword from the memory a plurality of times, wherein each of the read operations uses a different one of the plurality of read reference voltages selected based on the rankings of the plurality of read reference voltages. The performance metric comprises, for example, a bit error rate, a bit polarity disparity, a substantially minimal syndrome weight and/or measures of an average system latency or a tail latency. The ranking is optionally based on a size of the page populations that had each of the ranked read reference voltages. Channel estimation is performed separately for each of the plurality of page populations.
Type:
Grant
Filed:
July 8, 2016
Date of Patent:
February 7, 2017
Assignee:
Seagate Technology LLC
Inventors:
AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Thuy Van Nguyen, Ludovic Danjean, Erich F. Haratsch
Abstract: There is disclosed an apparatus and method for supporting storage devices during manufacture. The apparatus includes structural members and plural slot carriers received in bays in the apparatus. Each slot carrier carries at least one slot arranged to receive a storage device, wherein the slot carriers are insertable and/or removable from the bays through apertures at the front of the apparatus. Clamp assemblies are arranged to releasably clamp the slot carrier to one or more structural members at the sides of the slot carrier.
Abstract: A magnetic data storage medium capable of storing data bits may be configured at least with a magnetic underlayer structure and a recording structure. The recording structure can have at least a first magnetic layer and a second magnetic layer with the first magnetic layer decoupled by being constructed of an alloy of cobalt, platinum, and a platinum group metal element.