Patents Assigned to Seagate Technology
-
Patent number: 10191676Abstract: The disclosure is directed to protecting data of a scalable storage system. A scalable storage system includes a plurality of nodes, each of the nodes having directly-attached storage (DAS), such as one or more hard-disk drives and/or solid-state disk drives. The nodes are coupled via an inter-node communication network, and a substantial entirety of the DAS is globally accessible by each of the nodes. The DAS is protected utilizing intra-node protection to keep data stored in the DAS reliable and globally accessible in presence of a failure within one of the nodes. The DAS is further protected utilizing inter-node protection to keep data stored in the DAS reliable and globally accessible if at least one of the nodes fails.Type: GrantFiled: February 22, 2017Date of Patent: January 29, 2019Assignee: Seagate Technology LLCInventors: Earl T. Cohen, Robert F. Quinn
-
Patent number: 10192575Abstract: An apparatus includes at least one actuator shaft. First and second head stack assemblies are coaxially located on the actuator shaft(s). The first and second head stack assemblies each include: at least one bearing having an inner race coupled to an outer surface of the actuator shaft(s); an E-block surrounding an outer race of the at least one bearing; an annular gap is between the E-block and the outer race of the at least one bearing; a ring of bonding material filling the annular gap; and an access gap providing a fluid path to the annular gap from at least one of a top and a bottom of the E-block.Type: GrantFiled: October 31, 2017Date of Patent: January 29, 2019Assignee: Seagate Technology LLCInventor: Roger A. Resh
-
Patent number: 10186292Abstract: A recording head has a waveguide core layer that delivers light from a light source to a region proximate a magnetic write pole. A near-field transducer is formed of a thin film of Rh or Ir deposited over the waveguide core layer. The near-field transducer includes an enlarged part with two straight edges facing a media-facing surface and at obtuse angles relative to the media-facing surface. A peg extends from the enlarged part towards the media-facing surface. The waveguide core layer has a terminating end with terminating edges that align with the two straight edges of the near-field transducer.Type: GrantFiled: April 30, 2018Date of Patent: January 22, 2019Assignee: Seagate Technology LLCInventors: Vivek Krishnamurthy, Tae-Woo Lee, Michael Allen Seigler, Peng Zhang
-
Patent number: 10183376Abstract: Embodiments of the present disclosure include carriers for a row bar or stack of row bars to be lapped. In some embodiments, the ratio of the coefficient of thermal expansion of at least the bridge of a carrier to the coefficient of thermal expansion of the slider row bar or stack of slider row bars is less than 1.6. In some embodiments, a carrier can include a bridge having a length longer than the row bar or stack of row bars. In some embodiments, one or more bridge bending members can have junction centerlines offset from the corresponding bridge bending members.Type: GrantFiled: October 20, 2016Date of Patent: January 22, 2019Assignee: Seagate Technology LLCInventors: Yuhong Xiong, Joel W. Hoehn, Yeoh Hooi Sze, Ng Kok Cheong
-
Patent number: 10186285Abstract: A data reader may consist of at least a magnetoresistive stack positioned on an air bearing surface. A portion of the magnetoresistive stack may be set to a first fixed magnetization by a pinning structure separated from the air bearing surface by a front shield that is set to a second fixed magnetization by a biasing structure. The front shield may be separated from the biasing structure by a coupling structure.Type: GrantFiled: April 20, 2017Date of Patent: January 22, 2019Assignee: Seagate Technology LLCInventors: Adam A. Lapicki, Sameh Hassan, YuQing Du, Mark T. Kief, Marcus W. Ormston
-
Patent number: 10186283Abstract: A method of forming a peg of a NFT, the peg having a tapered portion, the method including depositing a layer of dielectric material; forming a three dimensional shape from at least a portion of the dielectric material the three dimensional shape having two side surfaces and two end surfaces; and depositing plasmonic material on at least one side surface of the three dimensional shape of dielectric material, wherein the plasmonic material deposited on the at least one side surface forms the tapered portion of the peg.Type: GrantFiled: November 11, 2015Date of Patent: January 22, 2019Assignee: Seagate Technology LLCInventors: Sridhar Dubbaka, YongJun Zhao, David Michael Grundman
-
Patent number: 10180868Abstract: Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.Type: GrantFiled: June 30, 2017Date of Patent: January 15, 2019Assignee: Seagate Technology LLCInventors: AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Erich F. Haratsch
-
Patent number: 10180792Abstract: Data storage devices may store selected data received from a data source to a buffer memory. The selected data may be copied from the buffer to a non-volatile memory configured for sequential storage. The selected data may then be copied from the buffer to a solid state memory, such as dynamic random access memory. The selected data may be copied from the solid state memory to a main store, such as a magnetic disc memory. If the selected data cannot be found in the solid state memory, the selected data in the non-volatile memory can be copied to the main store.Type: GrantFiled: April 30, 2015Date of Patent: January 15, 2019Assignee: Seagate Technology LLCInventors: Mark Gaertner, James D Sawin
-
Patent number: 10176212Abstract: Systems and methods are disclosed for management of a tiered storage system by a top tier storage device. In some embodiments, an apparatus may comprise a circuit configured to maintain an address map at a first storage tier, receive a read request for specified data, return the specified data when the data exists on the first storage tier, and when the specified data does not exist on the first storage tier, return an indication to query a second storage tier. The circuit may be further configured to determine infrequently accessed cold data stored to the first tier, provide to a host device a copy of the cold data stored in an area of the first storage tier scheduled for defragmentation, and perform the defragmentation operation, including copying valid data to an available area of the first storage tier, the valid data not including the cold data.Type: GrantFiled: October 15, 2014Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventor: Thomas R Prohofsky
-
Patent number: 10176886Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.Type: GrantFiled: July 7, 2017Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventors: Thomas V. Spencer, Ryan James Goss, Mark A. Gaertner
-
Patent number: 10177771Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.Type: GrantFiled: October 3, 2017Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventors: Jason Bellorado, Marcus Marrow, Zheng Wu
-
Patent number: 10177791Abstract: An apparatus may include a circuit that performs one or more read and recovery operations for one or more data segments including updating an outer code syndrome for one or more recovered data segments recovered by the one or more read and recovery operations and preventing updates of the outer code syndrome for one or more failed data segments not recovered by the one or more read and recovery operations.Type: GrantFiled: November 8, 2016Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventors: Deepak Sridhara, Ara Patapoutian
-
Patent number: 10176833Abstract: A folded lasing cavity comprises at least one bend. The folded lasing cavity is disposed on and configured to emit light along a substrate-parallel plane. An etched facet is on an emitting end of the folded lasing cavity and an etched mirror is on another end of the folding lasing cavity. An etched shaping mirror redirects light received from the etched facet in a direction normal to the substrate-parallel plane.Type: GrantFiled: January 18, 2017Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventors: Roger L. Hipwell, Jr., Scott Eugene Olson
-
Patent number: 10176832Abstract: A bond pad set includes at least one ground pad and at least one electrical bond pad configured to bias and send/receive signals. The bond pad set is electrically connected to a multiplicity of electrical components. At least one electrical bond pad of the bond pad set is shared between two or more of the electrical components.Type: GrantFiled: January 12, 2018Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventors: Jason Bryce Gadbois, Declan Macken, Karsten Klarqvist
-
Patent number: 10170140Abstract: A write head comprises a waveguide core configured to receive light emitted in a crosstrack direction from a light source at a fundamental transverse electric (TE00) mode. The waveguide core comprises a first turn that receives the light in the crosstrack direction redirects the light to an opposite crosstrack direction and a second turn that redirects the light to a direction normal to a media-facing surface of the write head. The waveguide core comprises a straight section that couples the first and second turns and a branched portion extending from the straight section. The branched portion is configured to convert the light to a higher-order (TE10) mode. A near-field transducer at the media-facing surface is configured to receive the light at the TE10 mode from the waveguide and directs surface plasmons to a recording medium in response thereto.Type: GrantFiled: January 23, 2017Date of Patent: January 1, 2019Assignee: Seagate Technology LLCInventors: Reyad Mehfuz, Aidan Dominic Goggin, Kelly Elizabeth Hamilton, John Bernard McGurk
-
Patent number: 10169232Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.Type: GrantFiled: February 19, 2016Date of Patent: January 1, 2019Assignee: Seagate Technology LLCInventors: Horia Cristian Simionescu, Balakrishnan Sundararaman, Shashank Nemawarkar, Larry Stephen King, Mark Ish, Shailendra Aulakh
-
Patent number: 10171110Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.Type: GrantFiled: July 3, 2017Date of Patent: January 1, 2019Assignee: Seagate Technology LLCInventors: Jeffrey John Pream, Eric Michael Beck
-
Patent number: 10163456Abstract: A near-field transducer is situated at or proximate an air bearing surface of the apparatus and configured to facilitate heat-assisted magnetic recording on a medium. The near-field transducer includes an enlarged region comprising plasmonic material and having a first end proximate the air bearing surface. The near-field transducer also includes a disk region adjacent the enlarged region and having a first end proximate the air bearing surface. The disk region comprises plasmonic material. A peg region extends from the first end of the disk region and terminates at or proximate the air bearing surface. The near-field transducer further includes a region recessed with respect to the peg region. The recessed region is located between the peg region and the first end of the enlarged region.Type: GrantFiled: October 23, 2015Date of Patent: December 25, 2018Assignee: Seagate Technology LLCInventors: Weibin Chen, Werner Scholz
-
Patent number: 10162393Abstract: As may be implemented in accordance with one or more embodiments, an electrical connector such as a low-temperature co-fired ceramic (LTCC) connector is sealed to an opening in a base deck having bottom and/or side walls that define a cavity. A mechanical component is coupled to balance forces applied to opposing surfaces of the electrical connector, which can mitigate the application of high forces to connector pins and/or to the connector itself. Further, this balancing may be implemented to maintain a controlled bias force against the connector. The electrical connector may, for example, be hermetically sealed to the opening by a seal such as a gasket, epoxy or other material, which may be included in the electrical connector.Type: GrantFiled: January 13, 2016Date of Patent: December 25, 2018Assignee: Seagate Technology LLCInventors: Tave Joseph Fruge, Frank William Bernett, John Francis Fletcher, Richard K. Thompson
-
Patent number: 10164760Abstract: Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.Type: GrantFiled: October 18, 2016Date of Patent: December 25, 2018Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu