Patents Assigned to Seagate Technology
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Patent number: 10164709Abstract: A system includes a first optical communication interface and a second optical communication interface optically coupled via a free-space communication channel. The interfaces are spaced at variable distances. Each interface includes an optical source to provide a beam of electromagnetic energy and an optical receiver to receive the beam to bi-directionally communicate with the other interface via the channel. The first optical communication interface may be coupled to a sub-chassis. The second optical communication interface may be coupled to a device frame. The device frame may be movably coupled to the chassis. Communication may utilize multi-input, multi-output processing configured by a calibration matrix. A shutter may be positioned to receive the beam or be positioned clear of the beam depending on the distance between the interfaces.Type: GrantFiled: April 7, 2017Date of Patent: December 25, 2018Assignee: Seagate Technology LLCInventors: Richard C. A. Pitwon, David Michael Davis
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Patent number: 10164592Abstract: A preamplifier may have a freeze bit that when set, puts the preamplifier in a static state, which prevents the preamplifier from implementing subsequent programming commands. The freeze state may continue until an unfreeze bit is programmed. In a multiple preamplifier system, preamplifiers can be differently and individually configured over a single interface. Preamplifiers may be released from the static state (frozen) by either programming the unfreeze bit (which can release all of the preamps) or by programming the freeze bit to a “0” state (releases the individual preamp). An inversion control circuit can allow inversion of a control signal to a preamplifier. The inversion control circuit may be enabled and disabled based on a physical conductive connection to a logic high voltage or a logic low voltage. One or more programmable control lines can determine whether the inversion function is activated when the inversion control circuit is enabled.Type: GrantFiled: August 24, 2015Date of Patent: December 25, 2018Assignee: Seagate Technology LLCInventors: Robert Matousek, Todd Michael Lammers, Thomas Lee Schick
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Publication number: 20180367164Abstract: An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.Type: ApplicationFiled: October 25, 2017Publication date: December 20, 2018Applicant: Seagate Technology LLCInventors: Marcus Marrow, Jason Bellorado, Vincent Brendan Ashe, Rishi Ahuja
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Publication number: 20180366149Abstract: An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.Type: ApplicationFiled: October 25, 2017Publication date: December 20, 2018Applicant: Seagate Technology LLCInventors: Jason Bellorado, Marcus Marrow
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Publication number: 20180366155Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.Type: ApplicationFiled: October 23, 2017Publication date: December 20, 2018Applicant: Seagate Technology LLCInventors: Jason Bellorado, Marcus Marrow, Zheng Wu
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Publication number: 20180366156Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.Type: ApplicationFiled: October 2, 2017Publication date: December 20, 2018Applicant: Seagate Technology LLCInventors: Marcus Marrow, Jason Bellorado, Zheng Wu
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Patent number: 10157631Abstract: A slider includes an array of two or more transducer sets offset from one another in a cross-track direction. Each transducer set includes at least one writer and at least one reader. All of the transducer sets are configured to operate simultaneously to perform any combination of reading and writing on two or more tracks of a recording medium. At least one actuator is included between two the transducer sets. The actuator is configured to adjust a cross-track spacing between the two transducer sets in response to a control current.Type: GrantFiled: January 17, 2018Date of Patent: December 18, 2018Assignee: Seagate Technology LLCInventors: Jon D. Trantham, Jason Bryce Gadbois, Mehmet Faith Erden
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Patent number: 10157637Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.Type: GrantFiled: October 2, 2017Date of Patent: December 18, 2018Assignee: Seagate Technology LLCInventors: Marcus Marrow, Jason Bellorado, Zheng Wu
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Patent number: 10151978Abstract: Provided herein is a method, including creating a first layer over a substrate, wherein the first layer is configured for directed self-assembly of a block copolymer thereover; creating a continuous second layer over the first layer by directed self-assembly of a block copolymer, wherein the second layer is also configured for directed self-assembly of a block copolymer thereover; and creating a third layer over the continuous second layer by directed self-assembly of a block copolymer. Also provided is an apparatus, comprising a continuous first layer comprising a thin film of a first, phase-separated block copolymer, wherein the first layer comprises a first chemoepitaxial template configured for directed self-assembly of a block copolymer thereon; and a second layer on the first layer, wherein the second layer comprises a thin film of a second, phase-separated block copolymer.Type: GrantFiled: November 18, 2014Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: XiaoMin Yang, Shuaigang Xiao, Kim Y. Lee, David S. Kuo
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Patent number: 10151025Abstract: The embodiments disclose an apparatus including at least two carbon source deposition tools for emitting electrons, at least two reflective polarity rear button permanent magnets integrated into the carbon source deposition tools for reflecting emitted electrons, and at least two paired polarity Helmholtz coils integrated into the carbon source deposition tools for forming uniform parallel magnetic field lines for confining the emitted electrons to uniformly deposit carbon onto the surfaces of a two-sided media disk.Type: GrantFiled: July 31, 2014Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: Christopher Loren Platt, Zhaohui Fan, Samuel Lewis Tanaka, Chun Wai Joseph Tong, Thomas Larson Greenberg, Xiaoding Ma
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Patent number: 10152249Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.Type: GrantFiled: September 21, 2016Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventor: Jon David Trantham
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Patent number: 10152457Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.Type: GrantFiled: October 25, 2016Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10152422Abstract: A method of adjusting asynchronous cache operations on a cache device includes accessing the cache device each cache window having a plurality of cache blocks, and each cache block having corresponding metadata indicating a status of the cache block. The method also includes receiving, at a first cache block, a first input/output operation and updating a first metadata of the first cache block, the first metadata being marked as dirty. The method also includes receiving, at a second cache block, a second input/output operation and updating a second metadata of the second cache block, the second metadata being marked as dirty. The method also includes grouping, in a page, the first and second input/output operations and updating, in a single operation according to the page, the first and second cache blocks according to the first and second input/output operations. The first and second metadata are then marked as non-dirty.Type: GrantFiled: June 13, 2017Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventor: Kishore Sampathkumar
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Patent number: 10152997Abstract: Systems and methods of laser bias calibration are presented. A preamplifier circuit may configure a laser current supplied to a laser emitter to be a first laser current of the plurality of laser currents during the writing of one or more first sectors. The preamplifier may further detect one or more gaps in a write power signal while the laser current of the laser emitter is configured to be the first laser current. In response to the detection of the one or more gaps in the write power signal, the preamplifier may configure the laser current supplied to the laser emitter to be a second laser current of the plurality of laser currents during the writing of one or more second sectors. The preamplifier circuit may be utilized in a heat assisted magnetic recording device.Type: GrantFiled: July 26, 2017Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: Alfredo Sam Chu, Todd Michael Lammers, Thomas Lee Schick, Robert Matousek
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Patent number: 10152998Abstract: Provided herein is an apparatus including an imaging lens assembly configured to collect reflected light from a surface of an article; an image sensor configured to receive reflected light from the imaging lens assembly, wherein the imaging lens assembly and the image sensor are each arranged at different angles for focusing on substantially an entire surface of an article; and a processing means configured to process signals from the image sensor corresponding to polarized reflected light and subsequently generate one or more features maps.Type: GrantFiled: May 16, 2014Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: David M. Tung, Joachim Walter Ahner
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Patent number: 10152236Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, the storage device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A local volatile memory has separate HDD and SSD partitions respectively accessible by the HDD and SSD controller circuits. A top level controller circuit performs a cleaning operation to transfer a data set from the non-volatile solid state memory to the rotatable storage media by issuing a read command to the HDD controller circuit to retrieve the data set to the HDD partition, transferring the data set from the HDD partition to the SSD partition, and issuing a write command to the SSD controller circuit to write the data set from the SSD partition to the non-volatile solid state memory.Type: GrantFiled: February 15, 2018Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: John Edward Moon, Leata Blankenship, Greg Larrew, Stanton M. Keeler
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Publication number: 20180349040Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: Seagate Technology LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Patent number: 10147445Abstract: One or more detectors detect data from respective one or more analog sources operable to read from a storage medium. A buffer pool is between the decoders and two or more detectors. The decoders are simultaneously operable, via the buffer pool, to independently decode the data from the one or more detectors.Type: GrantFiled: November 28, 2017Date of Patent: December 4, 2018Assignee: Seagate Technology LLCInventors: Bruce Douglas Buch, Mark Allen Gaertner, Jon D. Trantham, Mehmet Fatih Erden
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Patent number: 10147448Abstract: A tray system for containing multiple electronic components that includes a first tray having a planar member and a plurality of pockets recessed into an upper surface of the planar member, wherein each of the pockets includes: a bottom surface; an aperture extending through the bottom surface; a supply channel extending from a lower surface of the planar member to the aperture; a plurality of wall segments extending from the bottom surface of the pocket to the upper surface of the planar member and defining a perimeter of the pocket; and a plurality of pedestals extending from the bottom surface of the pocket toward the upper surface of the first tray.Type: GrantFiled: July 7, 2015Date of Patent: December 4, 2018Assignee: Seagate Technology LLCInventors: Lijuan Zhong, Peter Gunderson
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Patent number: D836133Type: GrantFiled: December 29, 2015Date of Patent: December 18, 2018Assignee: Seagate Technology LLCInventors: Richard Silverstein, Sarah Nguyen