Patents Assigned to SECURE-IC SAS
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Patent number: 10855476Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.Type: GrantFiled: July 1, 2016Date of Patent: December 1, 2020Assignee: SECURE-IC SASInventors: Rachid Dafali, Jean-Luc Danger, Sylvain Guilley, Florent Lozac'h
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Patent number: 10735179Abstract: A computer implemented method, program product, and system implementing said method, for transforming a call graph representation of an algorithm into a secured call graph representation of said algorithm. The call graph comprises inputs (a, b, f), internal variables being the edges of the graph (c, d, e), elementary functions being the nodes of the graph, said functions being either linear or not linear, and outputs (g), the method comprising: a step of masking each input of the call graph, a step of replacing each unmasked internal variable of the call graph with a masked variable, a step of replacing at least each non-linear function of the call graph with an equivalent function that applies to masked variables, a step of unmasking each output of the call graph.Type: GrantFiled: February 16, 2018Date of Patent: August 4, 2020Assignee: SECURE-IC SASInventors: Philippe Nguyen, Sylvain Guilley
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Patent number: 10691855Abstract: Devices, methods, and computer program products for detecting Points Of Failures in an integrated circuit (IC) are provided. The integrated circuit device is described by a structural description (2) comprising a plurality of elements, the elements representing cells and wires interconnecting the cells, the structural description further comprising portions representing a set of sensitive functional blocks (16), each sensitive functional block comprising one or more inputs, at least one sensitive output, and a set of elements interconnected such that the value of the sensitive output is a Boolean function of the input values of the sensitive functional block.Type: GrantFiled: March 27, 2018Date of Patent: June 23, 2020Assignee: SECURE-IC SASInventors: Sylvain Guilley, Théophile Boue
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Patent number: 10652033Abstract: There is disclosed a method of handling a sensor, comprising the steps of: defining a subset of sensor components of the sensor; challenging said subset under uniform conditions; receiving output signal values from said subset; for each component of the subset, determining the statistical moment of order i of the temporal distribution of the output signal value of said each sensor component; determining one or more outliers sensor components, said outliers sensor components being components whose ith order statistical moment has a difference with the mean value of the spatial distribution of the chosen moment over the subset superior in absolute value to a threshold, the ith order statistical moment of one sensor component being estimated on the temporal distribution associated to this sensor component. Developments describe in particular the use of imaging sensors, key generation, authentication, helper data files and the handling of videos.Type: GrantFiled: October 16, 2018Date of Patent: May 12, 2020Assignee: SECURE-IC SASInventors: Adrien Facon, Sylvain Guilley
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Patent number: 10630492Abstract: There is provided a method for testing a Physically Unclonable Function (PUF) implemented in a device, said PUF being configured to receive at least one challenge, each challenge comprising a set of bits, and to produce a set of responses, each response comprising at least one bit and corresponding to one challenge, said PUF comprising a circuitry including a set of PUF elements, each PUF element being controlled by at least one input bit corresponding to at least one bit of said challenge, wherein the method comprises the steps of: applying at least one bit of the challenge to the PUF instance; determining (300) identifiers for at least some of the PUF elements, the identifier of each PUF element being determined from the response output by said PUF element in response to said at least one bit of the challenge; applying a statistical randomness test (304) to a group of identifiers comprising at least some of the identifiers determined for said PUF elements, which provides a test indicator; and testing saiType: GrantFiled: April 6, 2017Date of Patent: April 21, 2020Assignee: SECURE-IC SASInventors: Sylvain Guilley, Jean-Luc Danger, Philippe Nguyen
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Patent number: 10607006Abstract: There is disclosed a system for monitoring the security of a target system (110) with a circuit (120), the target system (110) comprising at least one processor (111) and wherein: the circuit (120) comprises a finite-state machine (122) configured to receive data from one or more sensors (130) distributed in the target system (110), at least one sensor (1303) being located on the processor (111) of the target system (110); the finite-state machine (122) is configured to determine a state output in response to data received from sensors (130); the system monitoring the security based on said state output. Developments describe the use of a self-alarm mechanism comprising an encoder to encode states with redundancy, the application of an error correction code, comparisons with predefined valid encoded states, the triggering of an alarm to the processor, the determination of actions and/or retroactions on sensors and/or diagnostics and countermeasures.Type: GrantFiled: July 27, 2017Date of Patent: March 31, 2020Assignee: SECURE-IC SASInventors: Jean-Luc Danger, Sylvain Guilley, Thibault Porteboeuf
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Patent number: 10571313Abstract: There is provided a calibration device for calibrating a digital sensor (3), said digital sensor being configured to protest a target digital circuit (30) fed by a clock signal having a clock period by triggering an alarm depending on a condition between said clock signal and an optimal alarm threshold, said optimal alarm threshold being determined by minimizing a quantity depending on the probability of occurrence of false positives and on the probability of occurrence of false negatives.Type: GrantFiled: June 26, 2015Date of Patent: February 25, 2020Assignee: SECURE-IC SASInventors: Sylvain Guilley, Thibault Porteboeuf
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Patent number: 10461922Abstract: There is provided a device or a method for executing an operation of a cryptographic scheme, the operation being applied to a given state of a data block of original data, the operation being defined in a basis ring corresponding to the quotient of a starting ring by a basis ideal generated by at least one element of the starting ring. The operation is executed from a state derived from the current state of the data block, in at least one reference ring, which provides a reference value for each reference ring, each reference ring being the quotient of the starting ring by a reference ideal.Type: GrantFiled: December 27, 2016Date of Patent: October 29, 2019Assignee: SECURE-IC-SASInventors: Cédric Murdica, Sylvain Guilley
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Patent number: 10374790Abstract: The subject of the invention is a countermeasure method for an electronic component implementing a public-key cryptography algorithm on an elliptic curve E defined over a field and comprising an iterative scalar multiplication operation making it possible to obtain a point [k]P on the basis of a point P of the curve E and of an integer k that must remain secret, the electrical consumption of the electronic component being dependent on the value taken by at least one so-called critical point used during said operation to iteratively determine the point [k]P.Type: GrantFiled: February 12, 2015Date of Patent: August 6, 2019Assignee: SECURE-IC SASInventors: Cédric Murdica, Sylvain Guilley
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Patent number: 10361854Abstract: There is provided a modular multiplication device for performing a multiplication of a first multiplicand and a second multiplicand modulo a given modulus, each of the multiplicand comprising a given number of digits, each digit having a given word size.Type: GrantFiled: December 28, 2016Date of Patent: July 23, 2019Assignee: SECURE-IC SASInventors: Sylvain Guilley, Cédric Murdica
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Patent number: 10354064Abstract: According to the invention, there is provided a computer implemented method for controlling dynamically the execution of a code by a processing system, said execution being described by a control flow graph comprising a plurality of basic blocks composed of at least an input node and an output node, a transition in the control flow graph corresponding to a link between an output node of origin belonging to a first basic block and an input node of a second basic block, a plurality of initialization vectors being associated to the output nodes at the time of generating the code, an a priori control word being associated to each input node which is linked to the same output node of origin according the control flow graph, said a priori control word being precomputed at the time of generating the code by applying a predefined deterministic function F to the initialization vector associated to its output node of origin, the following steps being applied once the execution of the output node belonging to a first baType: GrantFiled: June 19, 2015Date of Patent: July 16, 2019Assignee: SECURE-IC SASInventors: Sylvain Guilley, Thibault Porteboeuf
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Patent number: 10331912Abstract: The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in: selecting a set of k elementary Boolean variables of the circuit as a function of predefined selection criteria, constructing a variable x represented by k bits by concatenation of the k selected variables in accordance with a chosen order, determining a binary code C comprising a set of code words and belonging to a given vector space and the supplementary code D of said binary code C as a function of a condition bearing on the dual distance of said supplementary code D, said binary code C having a length n and a size 2k, where k designates the number of bits representing said variable x; substituting the variable x in the structural description of the Boolean circuit with a protected variable z represented by n bits so that: any operation of writing on the variable xType: GrantFiled: July 30, 2015Date of Patent: June 25, 2019Assignee: SECURE-IC SASInventors: Sylvain Guilley, Thibaut Porteboeuf, Jean-Luc Danger
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Publication number: 20190123916Abstract: There is disclosed a method of handling a sensor, comprising the steps of: defining a subset of sensor components of the sensor; challenging said subset under uniform conditions; receiving output signal values from said subset; for each component of the subset, determining the statistical moment of order i of the temporal distribution of the output signal value of said each sensor component; determining one or more outliers sensor components, said outliers sensor components being components whose ith order statistical moment has a difference with the mean value of the spatial distribution of the chosen moment over the subset superior in absolute value to a threshold, the ith order statistical moment of one sensor component being estimated on the temporal distribution associated to this sensor component. Developments describe in particular the use of imaging sensors, key generation, authentication, helper data files and the handling of videos.Type: ApplicationFiled: October 16, 2018Publication date: April 25, 2019Applicant: SECURE-IC SASInventors: Adrien FACON, Sylvain GUILLEY
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Publication number: 20190121955Abstract: There is disclosed a method of handling a sensor, comprising the steps of: challenging a subset of sensor components under uniform conditions; receiving output signal values from said subset; for each component, determining the statistical moment of order i of the temporal distribution of the output signal value of said each sensor component; and determining one or more pathological sensor components whose sum of the distances of values to other components of the subset is greater than a threshold, the distance between two sensor components being determined by the difference of the ith statistical moment values of the two temporal distributions associated to the components obtained when challenging said subset under uniform conditions. Described developments comprise the use of imaging sensors, key or identifier generation, authentication mechanisms, determination of thresholds, use of helper data files, adjustments of light sources and/or beam shaping, handling of lossy compression and of videos.Type: ApplicationFiled: October 16, 2018Publication date: April 25, 2019Applicant: SECURE-IC SASInventors: Adrien FACON, Sylvain GUILLEY
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Publication number: 20180260564Abstract: There is disclosed a circuit for monitoring the security of a processor, wherein the circuit is configured to access a memory configured to store execution context data of a software program executed by the processor; to determine one or more signatures from said execution context data; and to compare said signatures with predefined signatures to monitor the security of the processor (110). Developments describe that context data can comprise control flow data, that a signature can comprise a hash value or a similarity signature, or that the integrity of signatures can be verified for example by using a secret key (e.g. obtained by random, or by using a physically unclonable function). Further developments describe various controls or retroactions on the processor, as well as various countermeasures if cyber attacks are determined.Type: ApplicationFiled: March 1, 2018Publication date: September 13, 2018Applicant: SECURE-IC SASInventor: Thibault PORTEBOEUF
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Publication number: 20180248682Abstract: A computer implemented method, program product, and system implementing said method, for transforming a call graph representation of an algorithm into a secured call graph representation of said algorithm. The call graph comprises inputs (a, b, f), internal variables being the edges of the graph (c, d, e), elementary functions being the nodes of the graph, said functions being either linear or not linear, and outputs (g), the method comprising: a step of masking each input of the call graph, a step of replacing each unmasked internal variable of the call graph with a masked variable, a step of replacing at least each non-linear function of the call graph with an equivalent function that applies to masked variables, a step of unmasking each output of the call graph.Type: ApplicationFiled: February 16, 2018Publication date: August 30, 2018Applicant: SECURE-IC SASInventors: Philippe Nguyen, Sylvain Guilley
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Publication number: 20180183589Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge.Type: ApplicationFiled: December 21, 2017Publication date: June 28, 2018Applicant: SECURE-IC SASInventors: Jean-Luc DANGER, Philippe NGUYEN
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Publication number: 20180183614Abstract: Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge. The system further comprises: A helper data generator (2) configured to generate a helper data comprising a set of bits, a bit of the helper data being generated in association with each applied challenge, the helper data generator being configured to generate each helper data bit from the physical variable difference provided by the PUF in response to the application of the associated challenge, the system further comprising a secret information generator (3) for extracting secret information from the helper data.Type: ApplicationFiled: December 21, 2017Publication date: June 28, 2018Applicant: SECURE-IC SASInventors: Jean-Luc DANGER, Philippe NGUYEN
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Publication number: 20180183613Abstract: There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.Type: ApplicationFiled: July 1, 2016Publication date: June 28, 2018Applicant: SECURE-IC SASInventors: Rachid DAFALI, Jean-Luc DANGER, Sylvain GUILLEY, Florent LOZAC?H
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Publication number: 20180032723Abstract: There is disclosed a system for monitoring the security of a target system (110) with a circuit (120), the target system (110) comprising at least one processor (111) and wherein: the circuit (120) comprises a finite-state machine (122) configured to receive data from one or more sensors (130) distributed in the target system (110), at least one sensor (1303) being located on the processor (111) of the target system (110); the finite-state machine (122) is configured to determine a state output in response to data received from sensors (130); the system monitoring the security based on said state output. Developments describe the use of a self-alarm mechanism comprising an encoder to encode states with redundancy, the application of an error correction code, comparisons with predefined valid encoded states, the triggering of an alarm to the processor, the determination of actions and/or retroactions on sensors and/or diagnostics and countermeasures.Type: ApplicationFiled: July 27, 2017Publication date: February 1, 2018Applicant: SECURE-IC SASInventors: Jean-Luc DANGER, Sylvain GUILLEY, Thibault PORTEBOEUF