Abstract: There is provided a method for testing a Physically Unclonable Function (PUF) implemented in a device, said PUF being configured to receive at least one challenge, each challenge comprising a set of bits, and to produce a set of responses, each response comprising at least one bit and corresponding to one challenge, said PUF comprising a circuitry including a set of PUF elements, each PUF element being controlled by at least one input bit corresponding to at least one bit of said challenge, wherein the method comprises the steps of: applying at least one bit of the challenge to the PUF instance; determining (300) identifiers for at least some of the PUF elements, the identifier of each PUF element being determined from the response output by said PUF element in response to said at least one bit of the challenge; applying a statistical randomness test (304) to a group of identifiers comprising at least some of the identifiers determined for said PUF elements, which provides a test indicator; and testing sai

Abstract: The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in: selecting a set of k elementary Boolean variables of the circuit as a function of predefined selection criteria, constructing a variable x represented by k bits by concatenation of the k selected variables in accordance with a chosen order, determining a binary code C comprising a set of code words and belonging to a given vector space and the supplementary code D of said binary code C as a function of a condition bearing on the dual distance of said supplementary code D, said binary code C having a length n and a size 2k, where k designates the number of bits representing said variable x; substituting the variable x in the structural description of the Boolean circuit with a protected variable z represented by n bits so that: any operation of writing on the variable x

Abstract: Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102) having a front surface (20) and a back surface (21), the IC device further comprising a front side part (101) arranged on the front surface of the substrate (102) and stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface (13). The system comprises an internal shield (12) arranged in a layer located below said data layer and a verification circuit configured to check the integrity of at least one portion of the internal shield.

Abstract: There is provided a device for executing an operation of a cryptographic scheme, the operation being applied to a given state of a data block of original data, the operation being defined in a basis ring corresponding to the quotient of a starting ring by a basis ideal generated by at least one element of the starting ring, the device comprising: a first execution unit (120) configured to execute the operation from a state derived from the current state of the data block, in at least one reference ring, which provides a reference value for each reference ring, each reference ring being the quotient of the starting ring by a reference ideal, and a second execution unit (122) configured to execute the operation from the state derived from the current state of the data block in at least one extended ring corresponding to one or more reference rings, which provides at least one extension value for each extended ring, each extended ring corresponding to one or more reference ring being the quotient of the start

Abstract: There is provided a modular multiplication device for performing a multiplication of a first multiplicand and a second multiplicand modulo a given modulus, each of the multiplicand comprising a given number of digits, each digit having a given word size.

Abstract: There is provided a calibration device for calibrating a digital sensor (3), said digital sensor being configured to protest a target digital circuit (30) fed by a clock signal having a clock period by triggering an alarm depending on a condition between said clock signal and an optimal alarm threshold, said optimal alarm threshold being determined by minimizing a quantity depending on the probability of occurrence of false positives and on the probability of occurrence of false negatives.

Abstract: According to the invention, there is provided a computer implemented method for controlling dynamically the execution of a code by a processing system, said execution being described by a control flow graph comprising a plurality of basic blocks composed of at least an input node and an output node, a transition in the control flow graph corresponding to a link between an output node of origin belonging to a first basic block and an input node of a second basic block, a plurality of initialization vectors being associated to the output nodes at the time of generating the code, an a priori control word being associated to each input node which is linked to the same output node of origin according the control flow graph, said a priori control word being precomputed at the time of generating the code by applying a predefined deterministic function F to the initialization vector associated to its output node of origin, the following steps being applied once the execution of the output node belonging to a first ba