Patents Assigned to Seiko Instruments Inc.
  • Patent number: 9259182
    Abstract: To improve product lifetime as well as to increase wearing feeling, maintainability and productivity, and to suppress manufacturing costs and expenses of the user. A portable electronic device 10 includes a device body 20 arranged inside a garment W and housing an electronic component and a fixing member 30A formed separately from the device body 20 and arranged outside the garment W, which fixes the device body 20 so as to be attached and detached to and from the garment W in a state of sandwiching the garment W between the fixing member 30A and the device bogy 20 from the other side of the garment W. The fixing member 30A is formed so as to be elastically deformed, which is formed in a ring shape surrounding the device body 20. Gaps are provided on both sides of the device body 20 in the radial direction of the fixing member 30A between an inner peripheral surface of the fixing member 30A and the device body 20.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: February 16, 2016
    Assignee: Seiko Instruments Inc.
    Inventors: Hideki Okuda, Dai Terasawa, Teruo Kato
  • Patent number: 9256208
    Abstract: The present invention is to provide a timepiece. The time piece comprises a ring-shaped mounting member formed of an elastic material and positioned between the annular shell and the ring-shaped bezel. The ring-shaped mounting member includes an engaging portion having a second engagement surface configured to engage with a first engagement surface formed in the annular shell to restrict the ring-shaped bezel from moving relative to the annular shell in a first axial direction to prevent the ring-shaped bezel from separating from the annular shell. The ring-shaped mounting member is deformable with a force, so that the second engagement surface can slide along the first engagement surface to release ring-shaped bezel from the annular shell.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: February 9, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Haruki Hiranuma, Masahiro Ishida
  • Patent number: 9252289
    Abstract: A non-volatile semiconductor memory device has a semiconductor substrate, an element isolation region disposed in a surface of the semiconductor substrate, a well region disposed along one principal surface of the semiconductor substrate, source and drain regions arranged in the well region, a gate oxide film arranged on the surface of the semiconductor substrate between the source region and the drain region, a floating gate disposed on the gate oxide film, and an insulating film disposed on a surface of the floating gate. A control gate is capacitively coupled to the floating gate disposed through intermediation of the insulating film. A resistive element is serially connected to the control gate. Write characteristics of the non-volatile semiconductor memory device are improved as a result of a delay effect of the resistive element serially connected to the control gate.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: February 2, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Ayako Inoue, Kazuhiro Tsumura
  • Patent number: 9247374
    Abstract: A terminal device has at least one measurement sensor for measuring a physical quantity of a measurement target. A control unit switches the measurement sensor, when activated, from a non-activated state to an activated state. An activation unit, which is driven at lower power consumption than the measurement sensor, activates the control unit when a physical quantity having a correlation with the physical quantity of the measurement target has satisfied a given activation condition.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: January 26, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Yutaka Tomimatsu, Takeshi Uchiyama, Manabu Oumi, Koichi Moriya, Yoko Shinohara, Masataka Shinogi
  • Patent number: 9245864
    Abstract: A BGA semiconductor package includes a semiconductor device adhered by adhesive to a substrate, and a conductive micro ball fitted into a through-hole provided in the substrate. A bonding wire electrically connects the semiconductor device and the micro ball to each other. An encapsulation member made of resin encapsulates the semiconductor device, the adhesive, part of the micro ball, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted. At least a part of a bottom surface of the micro ball has an exposed portion as an external connection terminal, which is exposed through the through-hole provided in the substrate as a bottom surface of the encapsulation member.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: January 26, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Noriyuki Kimura
  • Patent number: 9240498
    Abstract: Phosphate-based glass doped with copper ions having infrared blocking filter characteristics is formed into particles and is mixed with a transparent encapsulating resin to encapsulate a semiconductor element. The glass particles have a particle diameter four times or more as large as a wavelength of infrared radiation to be blocked. An optical semiconductor device can be obtained having a stable filter characteristics thereof even if an incident light angle changes and is resistant to moisture.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: January 19, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Hiroyuki Fujita, Sadao Oku, Koji Tsukagoshi, Keiichiro Hayashi
  • Patent number: 9240426
    Abstract: A photoelectric conversion device in which a parasitic capacitance between an optical signal common output line for commonly transmitting an optical signal and a control signal line and a parasitic capacitance between an initial voltage common output line for commonly transmitting an initial voltage and the control signal line in a plurality of photoelectric conversion units are substantially equal is provided. The control signal line is arranged so that the length of the wiring part of the control signal line in parallel with the optical signal common output line and the length of the wiring part of the control signal line in parallel with the initial voltage common output line are substantially equal and the distance between the control signal line and the optical signal common output line and the distance between the control signal line and the initial voltage common output line are substantially equal.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: January 19, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Masahiro Yokomichi
  • Patent number: 9235196
    Abstract: There are provided a constant voltage circuit that features low current consumption and stable operation, and an analog electronic clock provided with the constant voltage circuit. The constant voltage circuit includes a differential amplifier circuit which is turned on/off by a predetermined signal and which controls the voltage of a gate of an output transistor on the basis of a reference voltage and a feedback voltage that are received, a switch circuit which is connected to an output terminal of the differential amplifier circuit and which is turned on/off by a predetermined signal, and a voltage holding circuit which is connected between the gate of the output transistor and a power supply terminal and which has a resistor and a capacitor connected in series. An analog electronic clock provided with the foregoing constant voltage circuit that supplies a voltage to at least an oscillation circuit and a frequency division circuit.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: January 12, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Kotaro Watanabe, Makoto Mitani
  • Patent number: 9236732
    Abstract: Provided is a voltage regulator capable of suppressing an overshoot with low current consumption. A comparator of an overshoot detection circuit is activated only when a power supply fluctuation occurs, and the comparator outputs a signal for reducing an overshoot occurring in an output voltage. In a steady state, the comparator of the overshoot detection circuit is turned off to prevent the current from being consumed.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: January 12, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Takashi Matsuda, Fumimasa Azuma
  • Patent number: 9236727
    Abstract: Provided is a current mode step-down switching regulator which is capable of enhancing over-current limiting characteristics even when an over-current limiting function operates to reduce an output voltage. The current mode step-down switching regulator includes a pulse adjusting circuit. When an over-current is detected, a switching output signal is thinned out by the pulse adjusting circuit to be outputted in order to reduce an apparent oscillation frequency, thereby reducing an influence by response delay in an over-current detecting comparator.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: January 12, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Atsuo Fukui
  • Patent number: 9236747
    Abstract: Provided is an electronic device capable of supplying desired electric power to a load so as to operate the load even in a case where charged power is minute and a voltage increase rate of a capacitor, which increases by charge, is low. The electronic device includes: a power source which has supply power less than consumption power of the load; a capacitor to be charged with the supply power; and a charge/discharge control circuit which controls charging of the capacitor and consumption of charged power of the capacitor by the load, and the charge/discharge control circuit includes: a first node to which the supply power of the power source is supplied; and a circuit which charges the capacitor with the supply power from the first node.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: January 12, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Fumiyasu Utsunomiya, Takakuni Douseki, Ami Tanaka
  • Patent number: 9236792
    Abstract: A voltage regulator permits reduced current consumption by promptly and timely stopping the operation of an inrush current protection circuit immediately after the voltage regulator is started up. The voltage regulator has an output voltage detection circuit, which issues a detection signal to actuate the inrush current protection circuit when a low voltage at an output terminal is detected at the time of starting up the voltage regulator. When it is detected that the voltage at the output terminal has reached a predetermined level, the operation of the inrush current protection circuit is stopped and a power path of the output voltage detection circuit is cut off.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: January 12, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Socheat Heng
  • Patent number: 9235193
    Abstract: A temperature compensation-type balance includes a balance staff, and a balance wheel having a plurality of bimetal portions disposed in parallel to each other in a circumferential direction around a rotation axis of the balance staff. Connection members connect respective ones of the plurality of bimetal portions and the balance staff. Each bimetal portion is a layered body in which a first member and a second member are radially overlapped, and one end portion in the circumferential direction is a fixed end connected to a respective connection member and the other end portion in the circumferential direction is a free end. The first member is formed of a ceramic material, and the second member is formed of a metal material having a thermal expansion coefficient different from that of the first member.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 12, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Takashi Niwa, Masahiro Nakajima, Takuma Kawauchiya, Hisashi Fujieda, Manabu Shinke
  • Patent number: 9231101
    Abstract: A semiconductor device includes a semiconductor substrate, a body region, a body contact region and a cancelling region each of the first conductivity type, and a buried layer, an epitaxial layer and a source region each of the second conductivity type. A trench is provided in the epitaxial layer from a surface thereof. A gate insulating film is provided on an inner wall of the trench, and a gate electrode made of polycrystalline silicon is in contact with the gate insulating film and fills the trench. The cancelling region, which is provided below a bottom surface of the trench for cancelling a conductivity type of the buried layer, has a distribution center located below a boundary surface between the buried layer and the epitaxial layer. A trench bottom surface lower region of the first conductivity type is provided from the bottom surface of the trench continuously to the cancelling region.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 5, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Yukimasa Minami
  • Patent number: 9231766
    Abstract: An information processing device has a long-term registration system and a long-term signature system. The long-term registration system receives original data, sets attribute information with respect to the acquired original data, and associates the acquired original data with the set attribute information. The long-term signature system acquires long-term signature data obtained by performing a long-term signature on the associated original data and attribute information.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: January 5, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Shinichi Murao
  • Patent number: 9231081
    Abstract: In a method of manufacturing a semiconductor device, a body region is formed in an epitaxial layer provided on a semiconductor substrate. A part of a semiconductor material forming the body region surface is removed to form a convex-type contact region protruding from the body region surface and to form a shallow trench surrounding the convex-type contact region. A deep trench region is formed so as to extend from the shallow trench surface to inside of the epitaxial layer. A gate insulating film is formed on an inner wall of the deep trench region which is filled with polycrystalline silicon that is held in contact with the gate insulating film. A source region and a body contact region are formed in the shallow trench and the convex-type contact region, respectively, and a silicide layer is formed to connect the source region and the body contact region to each other.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 5, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Naoto Saitoh
  • Patent number: 9224872
    Abstract: A non-volatile memory circuit includes a non-volatile memory having a first source and drain region having a non-LOCOS offset structure and a second source and drain region having a LOCOS offset structure. A pair of switch circuits are connected in parallel to the respective first and second source and drain regions for switching voltages applied to the first and second source and drain regions so that the first source and drain region serves as a drain and the second source and drain region serves as a source in a writing mode, the second source and drain region serves as a drain and the first source and drain region serves as a source in a reading mode, and equal voltages are applied to the first source and drain region and the second source and drain region in a retention mode.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: December 29, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Ayako Kawakami
  • Patent number: 9219451
    Abstract: Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 22, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Tsutomu Tomioka
  • Patent number: D746469
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 29, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Hideki Okuda, Teruo Kato, Dai Terasawa
  • Patent number: D746987
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 5, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Hideki Okuda, Teruo Kato, Dai Terasawa