Abstract: A display apparatus including a substrate and having a first substrate electrode and a second substrate electrode, and light emitting sources disposed on the substrate and spaced apart from one another, the light emitting source including a light emitting structure having an n-type semiconductor layer, an active layer, and a p-type semiconductor layer, a p-type electrode electrically connected to the p-type semiconductor layer, an n-type electrode electrically connected to the n-type semiconductor layer, in which the first substrate electrode extends from an upper surface of the substrate facing the light emitting sources to a lower surface thereof and is electrically connected to the p-type electrode, the first substrate electrode including an upper portion having a substantially flat top surface and disposed on the upper surface of the substrate and a lower portion disposed on the lower surface of the substrate.

Abstract: Disclosed are a heat dissipation-electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate. The heat dissipation-electromagnetic shielding embedded packaging structure includes: a dielectric layer including an upper surface and a lower surface, wherein at least one hollow cavity unit is disposed inside the dielectric layer; an insulating layer disposed in the hollow cavity unit, wherein the hollow cavity unit is partially filled with the insulating layer; an electronic element, wherein one end is embedded in the insulating layer, the other end is exposed in the hollow cavity unit, and the electronic element includes terminals; a through hole penetrating through the upper surface and the lower surface of the dielectric layer and communicating with the terminals; and a metal layer covering the six surfaces of the dielectric layer and the interior of the through hole to form a shielding layer and circuit layer respectively.

Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.

Abstract: A method for remapping a virtual address to a physical address is provided. The method is used in an address remapping unit and includes: receiving, by a remapping processing unit of the address remapping unit, a remapping request, decoding the remapping request and determining whether the remapping request has a direct memory access (DMA) remapping request; and executing, by the remapping processing unit, a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address, when the remapping request has the DMA remapping request.

Abstract: A display apparatus including a display panel, a light source configured to emit light, and a light guide disposed on the light source and covering a side of the light source, the light source including a substrate, a light emitter including a light emitting stacked layer and disposed on the substrate, a light blocking layer disposed on a side surface of the light emitting stacked layer, and a reflector disposed between the substrate and the light guide, in which the light emitter has a first length direction and a second length direction, wherein orientation angles of the light emitter in the first and second length directions are different from each other, the substrate includes a first pad electrode and second pad electrode electrically connected to the light emitter, and the first and second pad electrodes are spaced apart from each other by at least 50 ?m.

Abstract: A voltage generation unit includes first to k-th amplifiers that individually receiving first to k-th reference voltages having mutually different voltage values, individually amplify these reference voltages with gain 1, and output the reference voltages. The generation unit generates plural gradation voltages by dividing voltages between respective voltages output from the first to k-th amplifiers. A decoder unit selects one gradation voltage corresponding to the luminance level represented by the pixel data piece among the gradation voltages and generates a signal having the one gradation voltage as the drive signal for driving a display device. Each amplifier includes a response-speed increase circuit that includes at least one transistor in which a source and a back gate are connected to an output terminal of the amplifier, a predetermined electric potential is applied to a drain, and the reference voltage received by the amplifier is received at a gate.

Abstract: A display apparatus device including a panel substrate including a circuit, and a light module including light sources each including a light emitter, a connection line, a light transmission layer on the light emitter, and a light block layer on the light transmission layer, in which the light sources includes first to fourth light sources, a transmission layer of the first light source includes a first converter, a transmission layer of the fourth light source includes a second converter, the first converter includes a wavelength converter to convert a first primary light of the first light source into a red color range, the second converter converts a fourth primary light of the fourth light source into a white light, and a peak wavelength of a second primary light of the second light source is different from that of a third primary light of the third light source.

Abstract: An embodiment relates to a surface emitting laser device and a light emitting device including the same. A surface emitting laser device according to the embodiment may include a first reflective layer; an active layer disposed on the first reflective layer; an aperture area disposed on the active layer and including an aperture and an insulating region; and a second reflective layer disposed in the aperture area. The active layer may comprise a plurality of quantum wells, quantum barriers, and intermediate layers disposed between the quantum wells and the quantum barriers. The quantum wells and the quantum barriers may include a ternary material, and the intermediate layers may comprise a binary material.

Abstract: Systems and methods for heterogenous hardware acceleration are disclosed. The systems and methods can include a neural network processing unit comprising compute tiles. Each of a first set of the compute tiles can include a first tensor array configured to support operations in a first number format. Each of a second set of the compute tiles can include a second tensor array configured to support operations in a second number format, the second number format supporting a greater range or a greater precision than the first number format, and a de-quantizer configured to convert data in the first number format to data in the second number format. The systems and methods can include neural network processing units, multi-chip hardware accelerators and distributed hardware accelerators including low-precision components for performing interference tasks and high-precision components for performing training tasks.

Abstract: The present disclosure relates to a device and a method for implementing live migration, where an on-chip system of the present disclosure is comprised in an integrated circuit apparatus, which comprises a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computing operations specified by users. The integrated circuit apparatus also comprises a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and other processing apparatuses and is used for storing data of the computation apparatus and other processing apparatuses.

Abstract: An embodiment provides a semiconductor device comprising: a semiconductor structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, and a plurality of first recesses and second recesses which extend through the second conductive semiconductor layer and the active layer and are arranged up to one region of the first conductive semiconductor layer, a first electrode disposed inside each of the first recesses and second recesses to be electrically connected to the first conductive semiconductor layer, and a second electrode electrically connected to the second conductive semiconductor layer, wherein the first conductive semiconductor layer, the active layer, the second conductive semiconductor layer include aluminum, and the number of most adjacent recesses in the plurality of second recesses is fewer than that in the plurality of first recesses and the plurality of second recesses include multiple recesses, each having an area larger than that of each

Abstract: An output short-circuit protection method, a power management chip and a switched-mode power supply are disclosed. When current accumulation has occurred in a power transistor, the number of consecutive current pulses during which the current accumulation occurred is counted. Upon the number of consecutive current pulses reaches a preset value, a regulation interval spanning switching periods is triggered, for at least some of the switching periods, the leading-edge blanking time is shortened or cancelled. In this way, an excessively large current flowing through the power transistor is prevented. Compared with existing fault response measures for power management chips, restart of the power supply and adjustment of the system timing are not needed, allowing easier implementation. Further, the automatic restart during chip start up due to false triggering as found in the existing measures for power management chips is circumvented.

Abstract: A display driver according to the present invention generates a plurality of driving voltages based on a video signal and applies the respective driving voltages to a plurality of source lines of a display panel. The display driver includes an overdrive part and an overdrive control circuit. The overdrive part executes an overdrive processing to increase amplitudes of the driving voltages. The overdrive control circuit detects an internal temperature of the display driver and stops the overdrive processing by the overdrive part when the temperature is higher than a predetermined temperature threshold.

Abstract: Disclosed are an area cleaning planning method for robot walking along the boundary, a chip and a robot. The area cleaning planning method includes: on a laser map which is scanned and constructed by a robot in real time, the robot is controlled to walk along the boundary in a predefined cleaning area framed at the current planning starting point position, so that the robot does not cross out the predefined cleaning area in the process of walking along the boundary; meanwhile, according to the division condition of the room cleaning subareas that conform to the preset wall environment condition in the predefined cleaning area, the robot is controlled to walk along the boundary in a matched area, when the robot walks along the boundary in the matched area and returns to the planning starting point position, the robot is controlled to perform planned cleaning in the matched area.

Abstract: A linear showerhead for growing GaN, including a first gas base, a second gas base, and a third gas base. First central gas passages are disposed in the middle of the first gas base. A first gap is disposed between two adjacent first central gas passages. A first nozzle is disposed at the bottom of a first central gas passage. The second gas base is disposed on the first gas base. Second central gas passages are disposed in the middle of the second gas base. A second gap is disposed between two adjacent second central gas passages. Two sides of a second central gas passage are provided with a second nozzle. The third gas base includes third central gas passages. A third central gas passage penetrates a first gap and a second gap. A third nozzle is disposed at the bottom of a third central gas passage.

Abstract: The present disclosure relates to a method of interconnecting semiconductor devices and an assembly of interconnected semiconductor devices. The method comprises forming a metal layer on a first connection surface of the first semiconductor device, and forming an oxidant layer on a second connection surface of the second semiconductor device, the first connection surface including first coupling pads, the second connection surface including the second coupling pads. The method further comprises aligning the first connecting pads and respective ones of the second connecting pads to each other, pressing together the metal layer and the oxidant layer, and reacting the metal layer with the oxidant layer under target condition to form a bonding layer. The bonding layer first regions, second regions, and third regions that are conductive regions, and a fourth region that is a nonconductive adhesive region. The method of interconnecting semiconductor devices allows alignment errors, improves yield, and reduces cost.

Abstract: A trench SiC MOSFET integrated with a high-speed flyback diode and a preparation method thereof are provided. The MOSFET is a trench structure, a trench-type gate-controlled diode is added in the vicinity of the MOSFET to solve the problem of electric field concentration at the bottom and corners of a trench, and P-type buried layers are added to the bottom of the trench to decrease the electric field intensity. Moreover, the gate-controlled diode and a body diode of the device are connected in parallel, so the on-voltage drop of the body diode is greatly decreased, thus reducing the loss in the reverse recovery mode. In addition, the gate-controlled diode is a unipolar device without the charge-storage effect, so the reverse recovery current of the body diode can be completely eliminated, thus reducing the dynamic loss.

Abstract: Disclosed in an embodiment are a semiconductor device and a light-emitting device package including same, the semiconductor device comprising: a substrate; a plurality of semiconductor structures arranged in a matrix shape in the central area of the substrate; passivation layers arranged on upper surfaces and lateral surfaces of the semiconductor structures and on the edge area of the substrate; a plurality of first wiring lines which are arranged at lower parts of the plurality of semiconductor structures and electrically connected thereto, and which include first end parts extending from the central area to the edge area of the substrate; a plurality of second wiring lines which are arranged at the lower parts of the plurality of semiconductor structures and electrically connected thereto, and which include second end parts extending from the central area to the edge area of the substrate; a plurality of first pads penetrating the passivation layer so as to be connected to the plurality of first end parts;

Abstract: A processor and an operating method thereof for renaming a destination logical register of a move instruction are provided. The processor comprises a plurality of physical registers and a renaming circuit. The renaming circuit is coupled to the plurality of physical registers and is configured to receive an instruction sequence and check the instruction sequence. When a current instruction of the instruction sequence comprises the move instruction, the renaming circuit assigns a first physical register, which is assigned to a source logical register of the current instruction previously, to the destination logical register of the current instruction. The first physical register is one of the plurality of physical registers.