Abstract: A battery monitoring system includes a first group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; a second group of a plurality of battery cells connected in series and including a third battery cell at a highest potential and a fourth battery cell at a lowest potential, the second group of the battery cells being connected to the first group of the battery cells in series; and first and second semiconductor devices capable of measuring a voltage of the first group of the battery cells and a voltage of the second group of the battery cells, respectively.

Abstract: A light emitting device including at least one main light emitting unit including a light emitting diode chip and a wavelength converter, and configured to emit white light, in which the light emitting diode chip includes at least one of an ultraviolet chip, a violet chip, and a blue chip, and the light emitting device is configured to be adjustable to emit light corresponding to a spectral power distribution of morning sunlight, light corresponding to a spectral power distribution of afternoon sunlight, and light corresponding to a spectral power distribution of evening sunlight.

Abstract: An out-of-order buffer includes an out-of-order queue and a controlling circuit. The out-of-order queue includes a request sequence table and a request storage device. The controlling circuit receives and temporarily stores the plural requests into the out-of-order queue. After the plural requests are transmitted to plural corresponding target devices, the controlling circuit retires the plural requests. The request sequence table contains m×n indicating units. The request sequence table contains m entry indicating rows. Each of the m entry indicating rows contains n indicating units. The request storage device includes m storage units corresponding to the m entry indicating rows in the request sequence table. The state of indicating whether one request is stored in the corresponding storage unit of the m storage units is recoded in the request sequence table. The storage sequence of the plural requests is recoded in the request sequence table.

Abstract: A pixel with multiple electroluminescent devices and shared electrodes is disclosed. In one embodiment of the present invention the pixel includes a top electrode, a bottom electrode, a first shared electrode, a second shared electrode, and three electroluminescent devices. The bottom electrode and the first shared electrode are coupled to and operates the first electroluminescent device. The first shared electrode and the second shared electrode are coupled to and operate the second electroluminescent device. The second shared electrode and the top electrode are coupled to and operate the third electroluminescent device.

Abstract: A display device including light emitting modules having signal lines and common lines arranged thereon, each including light emitting diodes mounted on an upper surface thereof and electrically connected to the signal lines and the common lines, respectively, a motherboard coupled to the light emitting modules, and a bonding layer having electrical conductivity and coupling the light emitting modules to the motherboard, in which each of the light emitting modules includes signal line terminals and common line terminals disposed on a lower surface thereof and electrically connected to the signal lines and the multiple common lines, respectively, and the motherboard includes board signal line terminals and board common line terminals disposed on an upper surface thereof at locations corresponding to the signal line terminals and the common line terminals of the light emitting modules.

Abstract: A gate trench and a source trench are formed simultaneously in the same etching process, a p-type semiconductor layer and a p-type doped region can be contacted in a self-aligned manner in the source trench, and the process is simple. A first insulating layer and a first gate are formed in a lower part of the gate trench, and a second insulating layer and a second gate are formed in an upper part of the gate trench so that the thick first insulating layer can protect the second gate from being easily broken down, the first gate can increase an electric field near a bottom of the gate trench, and thus a voltage withstand level of the semiconductor device can be improved. A bottom of the source trench can penetrate deep into a second n-type semiconductor layer.

Abstract: A communication configuration apparatus for constructing a communication topology structure based on a plurality of processing nodes may be included in a combined processing apparatus. The combined processing apparatus further includes an interconnection interface and other processing apparatus. The communication configuration apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the communication configuration apparatus and other processing apparatuses, respectively. The storage apparatus is used for storing data of the communication configuration apparatus and other processing apparatus. A technical solution of the present disclosure may improve efficiency of inter-chip communication.

Abstract: An embodiment relates to a surface-emitting laser element, a light-emitting device comprising same, and a method for manufacturing same. A surface-emitting laser element according to an embodiment may comprise: a substrate; a first reflective layer disposed on the substrate; an active layer disposed on the first reflective layer; an aperture region disposed on the active layer and including an aperture and an insulation region; and a second reflective layer disposed on the aperture region. The doping level of the aperture region may be (X+3)×XE18 (atoms/cm3) A ratio (b/a) of a second minimum diameter (b) to a first maximum diameter (a) of the aperture may be [95.0?(2X/3)]% to [99.9?(X/3)]%, wherein X may be 0 to 3.

Abstract: A method for wafer-level adjustment of protection circuits of electronic devices and a wafer for facilitating the same are provided. The method comprises: fabricating an adjustable terminal protection circuit for each of the electronic devices in the wafer; and adjusting each of the adjustable terminal protection circuits by cutting off one or more fuse elements in the one or more trimming circuits of the terminal protection circuit. The method provides a cost-effective approach to allow wafer-level on-chip adjustment of protection circuits for III-V compound devices in a flexible manner so as to address the issues of manufacturing process constrains under requirement of large wafer dimension.

Abstract: A method for a robot to judge whether the robot collides with a virtual wall, and a chip and the intelligent robot. The method comprises: providing pre-judgement regions on two sides of a virtual wall, so that when entering the pre-judgement regions, the robot can judge whether the robot collides with the virtual wall by combining a current direction of the robot as well as a relationship between a straight-line distance from the robot to a reference point and a straight-line distance from the reference point to a center point of the virtual wall.

Abstract: A detachable etching tool for etching a plurality of silicon carbide pieces has a first supporting column and a second supporting column, both of which are fixed through a tool fixing block. A bracket is arranged on the tool fixing block, and a limiting rod is installed on the lower end surface of the bracket. The bracket is inserted into the tool fixing block through the limiting rod and fixed on the tool fixing block with a fastening mechanism that comprises a base, a fixing seat, a telescopic spring, a telescopic guide column, a sliding block, a guide block, an inserting rod and a push-pull mechanism. The etching tool addresses low productivity per unit time and long time consumption in the etching processing.

Abstract: An interpolation filtering system implemented by a digital circuit is provided, it includes an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules.

Abstract: A power module and a power device are provided. The power device includes two screws, a heat dissipation components and a power module. The power module includes a substrate, a package body and two fixing structures. Each fixing structure includes a first through hole, two second through holes, an annular structure and two sinking structures. When the power module is fixed to the heat dissipation component, each sinking structure is bent toward the heat dissipation component, and each annular structure is fixed to the flat surface of the heat dissipation component by the screws. The heat dissipation surface of the substrate can be flatly attached to the flat surface of the heat dissipation component through the two fixed structures, so that the heat energy generated during the operation of the power module can be transferred out through the heat dissipation component.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are described herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on an active surface of each semiconductor device in addition to connection terminals. A plurality of second alignment solder parts are formed on a surface of the carrier board.

Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer; an ohmic contact disposed on the first nitride semiconductor layer; and a spacer disposed adjacent to a sidewall of the ohmic contact.

Abstract: A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

Abstract: A lighting device includes a substrate having a plurality of flat portions and a non-flat portion disposed between the flat portions, a plurality of light emitting sources disposed on the substrate, a fluorescent substrate layer covering one or more light emitting sources and converting a wavelength of a light from the light emitting source, and a connection line disposed on the substrate and electrically connecting the light emitting sources adjacent to each other between the adjacent light emitting sources. The substrate has a first end and a second end are arranged at different distance from a central axis.

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

Abstract: A proximity sensor is provided with multiple channels and a proximity sensor chip (IC) connected to the multiple channels through a sensing line. The proximity sensor chip (IC) includes an internal temperature sensor, senses a first sensing value through the multiple channels, senses a second sensing value through the internal temperature sensor, and compensates the first sensing value through addition or subtraction of the second sensing value with respect to the first sensing value. The internal temperature sensor includes: a clock signal generator including a first oscillator and generating first clock signals variable according to temperature characteristics; and a temperature compensator generating second clock signals according to a setting condition corresponding to the first clock signals generated from the clock signal generator and outputting the second sensing value by counting the second clock signals through a second oscillator generating reference clock signals independent of temperature change.