Abstract: A substrate for displays including a base, a plurality of first interconnects disposed on the base, a plurality of second interconnects disposed on the base to intersect with the first interconnects, and a plurality of sub-pixels disposed on the base and including one or more of the first and second interconnects, each of the sub-pixels including at least one interconnect extension protruding from at least one side of the second interconnect, first and second mounting portions formed between the at least one interconnect extension and the first interconnect, and a light emitting diode mounted on the first mounting portion, in which the second mounting portion is configured to mount another light emitting diode thereon.

Abstract: A flag holding circuit includes: a flag setting part connected to a voltage supply line and charging a capacitor according to an input signal; a flag determination part outputting an output signal based on a charging voltage of the capacitor; and a discharging part discharging the capacitor. The flag setting part includes: a switch having a first terminal connected to a connection line between the flag determination part and the discharging part and a second terminal connected to the voltage supply line or a grounding line according to a signal level of the input signal, and connecting or disconnecting the voltage supply line or the grounding line with the connection line according to a leakage control signal; and a switch control part, generating the leakage control signal whose signal level changes to be greater than a power supply voltage according to a clock signal and supplying it to the switch.

Abstract: A signal transmission device and a battery monitoring device are provided. The signal transmission device is connected to an operation device including an operation circuit for performing an operation based on a first voltage, a measurement circuit for obtaining measurement data based on the first voltage, and a process control circuit for operating based on a lower voltage and control an operation of the operation circuit based on the measurement data, and transmits and receives signals between the process control circuit and the measurement circuit. The signal transmission device includes a power reception circuit for supplying power from the power transmission circuit to the measurement circuit to acquire measurement data, and a power transmission circuit for transmitting the power from a process control circuit to the power reception circuit to receive the measurement data from the power reception circuit and supply the same to the process control circuit.

Abstract: The present disclosure provides a storage control method, a storage controller, a storage device, and a storage system. The storage control method controls a storage behavior of a storage device, including: acquiring behavior information of the storage device; processing the behavior information through a deep learning algorithm to obtain a behavior parameter of the storage device; and adjusting an operation mode of the storage device according to the behavior parameter of the storage device. The present disclosure enhances the automatic adjustment operation algorithm of the storage device by means of deep self-learning to adapt to the different requirements of the complex system for the storage device, thereby achieving the storage device with the optimal read/write performance, the best reliability, and the lowest power consumption in accordance with the requirements of the system.

Abstract: The present disclosure discloses a transistor structure and a method for manufacturing the same. The method includes: preparing a substrate, a plurality of gate structures are disposed on the substrate; forming a first spacer structure on both sidewalls of each gate structure; and forming a film layer, the film layer covers the substrate, the plurality of gate structures, the second spacer structure and the step structure. The present disclosure solves the problem that defects caused by growth speed differences of films at spacers of the gate structures and the substrate, such as deep pits or holes, occur in a film deposition process, thereby avoiding electricity leakage of a subsequent contact pipeline and failure of a device, thus ensuring the quality of the transistor product.

Abstract: The present invention relates to a method of detecting an access address of a physical channel in a Bluetooth signal to which channel coding is applied, the method including: performing initial signal processing in a unit of a specific length in a preamble section of a Bluetooth signal; and performing channel decoding in the specific length for a preamble part remained after the initial signal processing, wherein the specific length is a bit pattern length of a bitstream which is repeated in the preamble section or a length of a bitstream input for channel decoding. According to the present invention, channel decoding is performed in a unit of a bit pattern length of an access address from the remaining preamble part, and thus detection of the access address is available even though a start point of the access address is not provided.

Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.

Abstract: A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial layer disposed on the substrate, and a gate structure. The epitaxial layer has at least one trench formed therein, and the gate structure is disposed in the trench. A gate structure includes a lower doped region and an upper doped region disposed above the lower doped region to form a PN junction. The concentration of the impurity decreases along a direction from a peripheral portion of the upper doped region toward a central portion of the upper doped region.

Abstract: A display apparatus and a method of manufacturing the same are disclosed. The display apparatus includes at least one light emitting diode chip, a conductive portion disposed under the light emitting diode chip and coupled to the light emitting diode chip, and an insulating material surrounding the conductive portion. The conductive portion includes a first conductive portion and a second conductive portion, and the insulating material is formed to expose at least a portion of the upper surfaces of the first conductive portion and the second conductive portion.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer.

Abstract: A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.

Abstract: An FPGA chip-based handler simulation test system is provided. The FPGA chip-based handler simulation test system includes a handler simulator, a PC and a tester. The handler simulator includes an FPGA, an RS232 interface, a GPIB interface, a RAM, a LED, a keypad and a soft-core processor. The soft-core processor includes a CPU, an SDRAM, a PIO, a UART and a JTAG. The firmware of the soft-core processor establishes the communication of the RS232 interface and the GPIB interface, as well as the display of the LED and reception of the keypad. The test system of the present invention simulates handler communication by using a small-sized and low-cost hardware circuit, and is easy to carry. In this way, an operator can debug the handler in the laboratory without damaging the handler, thus protecting the expensive handler.

Abstract: A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.

Abstract: The invention relates to a method to reduce the contact resistance of ohmic contact in group III-nitride high-electron mobility transistor (HEMT). A heavily n-type doped nitride layer with modulation doping is epitaxially grown on selected contact regions for use as ohmic contact layer. The method for producing the n++ ohmic contact layer includes at least the following: deposition of nitride HEMT epitaxial structure on substrates (such as SiC, silicon, sapphire, GaN etc), deposition in-situ or ex-situ mask for selective growth of n-contact, selective etching to create of openings within the mask layer, deposition of modulation doped n++ nitride ohmic contact layer followed by ohmic metal deposition. The modulation doping involves alternating epitaxy of high and low doped nitride layers with common n-type dopant such as Ge, Si etc. The modulation doping significantly increases the range of n-type doping without detrimental effect on the material quality of the contact layer.

Abstract: The present disclosure includes but is not limited to the III-Nitride semiconductor devices including a barrier layer, a gallium nitride or indium gallium nitride channel layer having a Ga-face coupled with the barrier layer, and a patterned thermoconductive layer having a thermal conductivity of at least 500 W/(m-K) within 1000 nanometers of a Ga-face of the gallium nitride channel layer. The semiconductor device may be a high-electron-mobility transistor or a semiconductor wafer. Methods for making the same also are described.

Abstract: A memory device includes a memory control unit and a write output clock device. The memory control unit is used to provide a write input clock and a first control value. The write output clock device produces a plurality of internal clocks based on the write input clock, and selects a target internal clock from the plurality of internal clocks, and further delays the target internal clock to become a write output clock to a memory unit based on the first control value. The memory unit produces a data signal based on the write output clock. The memory control unit identifies whether the write output clock meets the time-sequence requirements of the memory unit. If the time-sequence requirements are not met, the memory control unit changes the first control value and/or changes the selected target internal clock to change the write output clock.

Abstract: The present disclosure provides a method for manufacturing semiconductor device and a semiconductor device formed using same. The method includes: preparing a substrate; forming a pad oxide layer and a barrier layer on the substrate, the barrier layer is disposed on the pad oxide layer; forming a plurality of shallow trench isolation structures in the substrate to form multiple regions in the substrate; removing a part of the barrier layer to form a recess, the recess is set in any one of the multiple regions, and a region directly below the recess is defined as a high voltage device region; and forming a gate oxide layer in the recess, and removing the barrier layer. The method provided in the present disclosure simplifies the manufacturing process and reduces the production costs.

Abstract: A light emitting diode package includes a housing including a body part, a first lead, a second lead, a light emitting diode chip, and a Zener diode. The body part has a cavity that is open at the top and has inclined side surfaces. The first lead and the second lead are supported by the housing and are disposed apart from each other so as to be electrically insulated. The light emitting diode chip is electrically connected to the first lead and the second lead and mounted within the cavity of the body part. The Zener diode is mounted on one side of the light emitting diode chip and inside the cavity of the body part.

Abstract: A displaying apparatus including: a panel substrate; a plurality of light emitting devices arranged on the panel substrate; and at least one connection tip disposed on one surface of each of the light emitting devices. Each of the light emitting devices includes a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first and second conductivity type semiconductor layers; and first and second electrode pads disposed on the light emitting structure.