Abstract: A network interface controller including a data alignment module, a boundary determination module and a checksum module is provided. The data alignment module receives raw data and re-combines the raw data as first valid data, wherein the raw data includes a first layer protocol segment and a second layer protocol segment. The boundary determination module receives the raw data in parallel to the data alignment module and performs a boundary determination operation on the raw data to generate a boundary information indicating a boundary between the first layer protocol segment and the second layer protocol segment. The checksum module is coupled to the data alignment module and configured to disassemble the first valid data as second valid data and calculate a checksum according to the boundary information and the second valid data.

Abstract: Disclosed is an insulated gate bipolar transistor (IGBT) power device, including a bipolar transistor, a first MOS transistor, a second MOS transistor, a body diode and a body region contact diode. An anode of the body region contact diode and an anode of the body diode are connected to the bipolar transistor. A first gate of the first MOS transistor is externally connected to a gate voltage of the IGBT power device and configured to control turning on and off of the first MOS transistor by means of the gate voltage of the IGBT power device. A second gate of the second MOS transistor is connected to an emitter voltage of the IGBT power device and configured to control turning on and off of the second MOS transistor by means of the emitter voltage of the IGBT power device.

Abstract: An output circuit is provided. The disclosure includes: a positive polarity voltage signal supplying circuit configured to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit configured to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch formed from a P channel transistor of which a source and a back gate are connected to the first node and a drain is connected to a first output terminal; a second switch formed from an N channel transistor of which a source and a back gate are connected to the second node and a drain is connected to the first output terminal; and third and fourth switches.

Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.

Abstract: Exemplary embodiments provide a semiconductor device including: a semiconductor structure which includes a first-conductive-type semiconductor layer, a second-conductive-type semiconductor layer, and an active layer disposed between the first-conductive-type semiconductor layer and the second-conductive-type semiconductor layer, wherein the semiconductor structure has a first recess passing through the second-conductive-type semiconductor layer, the active layer and a first portion of the first-conductive-type semiconductor layer; and a plurality of second recesses passing through the second-conductive-type semiconductor layer, the active layer and a second portion of the first-conductive-type semiconductor layer, wherein the first recess is disposed along an outer surface of the semiconductor structure, wherein the plurality of second recesses are surrounded by the first recess.

Abstract: A reference electrode including a casing through which one face at one side of a liquid junction that leaches an internal liquid is exposed. The casing is provided with an overhang portion that hangs out on the one face side of the liquid junction and prevents separation of the liquid junction from the casing; and an open portion that leaves a space on the one side of the liquid junction open toward a lateral direction along the one face.

Abstract: A bulb-type light source includes a globe transmitting a light and at least one light emitting device filament disposed in the globe. The light emitting device filament includes a substrate including n (n is a natural number equal to or greater than 2) flat portions and n?1 bendable portions disposed between the flat portions, a plurality of light emitting device chips disposed on the flat portions, a fluorescent substance layer covering each light emitting device chip and converting a wavelength of a light from each light emitting device chip, and a connection line disposed on the flat portions and electrically connecting the light emitting device chips adjacent to each other between the adjacent light emitting device chips.

Abstract: A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal isolated from the cell voltage measurement circuit; a plurality of protection elements each corresponding to each of the battery cells; and a protection circuit connected to the second terminal for discharging an electric current from the protection elements through the second terminal.

Abstract: A multi-segment linear LED drive circuit, device and method. A Multi-segment linear LED drive circuit includes a reference voltage input module, current source module, voltage control module, current regulation module, at least two LED light strings connected in series and at least two driving modules correspondingly. The reference voltage input module provides reference voltage for each of driving module; the current source module provides DC current for voltage control module; the voltage control module controls input voltage of driving module according to DC current; the driving module lights corresponding LED light string on or off according to reference voltage, input voltage and line voltage constant current; the current adjusting module adjusts constant current; constant current of rear driving module is greater than that of front driving module, and when current passes through rear driving module, front driving module stops driving, harmonic influence and circuit implementation cost are reduced.

Abstract: A interface circuit includes: a power supply circuit, configured to output a DC voltage; a voltage conversion circuit, configured to convert the DC voltage to a target voltage, wherein the voltage conversion circuit is a step-down conversion circuit; a first Type-C port and a second Type-C port, configured to be connected to the respective loads; a switch circuit, connected to the power supply circuit, the voltage conversion circuit, the first Type-C port and the second Type-C port respectively; and a USB controller, configured to communicate with the first Type-C port and the second Type-C port respectively, and regulate the DC voltage and the target voltage according to supply voltages of the loads connected to the first Type-C port and the second Type-C port, and control the switch circuit to apply the DC voltage or the target voltage to a Type-C port connected to a corresponding load.

Abstract: A power-on clear circuit includes a bias current generation circuit having one end connected to a first line supplied with a first power supply voltage, the other end connected to a second line kept at a fixed potential, and configured to generate a bias current, and to transmit the bias current to a first node; a first transistor having a first terminal connected to the second line, a second terminal connected to the first node, and a control terminal for receiving application of a second power supply voltage which varies to follow the first power supply voltage; an inverter unit configured to operate on the basis of the first power supply voltage, and to which a potential of the first node is input; and a signal outputting unit configured to output a power-on clear signal in accordance with an output of the inverter unit.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: A logic circuit includes an inverter that outputs from an output terminal a signal created by inverting the logic of a signal input into an input terminal, a first transistor that is connected to the input terminal in such a way as to maintain an OFF state, and a second transistor that is connected to the output terminal in such a way as to maintain an OFF state.

Abstract: A data compressor with a hash computing hardware configured to evaluate the hash value for the current hash key extracted from a source data string, obtain a hash line corresponding to the hash value from a hash table, and perform hash key comparison to find at least one matching hash key. The hash line includes a prefix address column that stores a prefix address. Each entry of the hash line is provided to store a hash key and an offset. The hash computing hardware evaluates an address of the at least one matching hash key by combining the prefix address and an offset of the at least one matching hash key, and the offset of the at least one matching hash key is obtained from an entry storing the at least one matching hash key.

Abstract: A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.

Abstract: An LED lighting apparatus including a rectifier to rectify AC voltages having different magnitudes and generate driving voltages corresponding to rectified voltages, a buck converter connected to an output terminal of the rectifier and generate an LED driving current corresponding to the driving voltages, a variable reference voltage comparator to receive the driving voltages, and generate variable reference voltages that fluctuate in correspondence to magnitudes of the output driving voltages, compare the driving voltages and the variable reference voltages, and output signals for controlling an operation of the buck converter, an LED including at least one LED group and driven by the LED driving current generated by the buck converter, and a controller including a converter controller to control the operation of the buck converter and a constant current controller to constant current-control the LED driving current applied to the at least one LED group.

Abstract: A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.

Abstract: A semiconductor device according to the embodiment may include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer; a first bonding pad disposed on the light emitting structure and electrically connected to the first conductivity type semiconductor layer; a second bonding pad disposed on the light emitting structure and spaced apart from the first bonding pad, and electrically connected to the second conductivity type semiconductor layer; and a reflective layer disposed on the light emitting structure and disposed between the first bonding pad and the second bonding pad. According to the semiconductor device of the embodiment, each of the first bonding pad and the second bonding pad includes a porous metal layer having a plurality of pores and a bonding alloy layer disposed on the porous metal layer.

Abstract: A microprocessor is configured for unchained and chained modes of split execution of a fused compound arithmetic operation. In both modes of split execution, a first execution unit executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and a second instruction execution unit receives the intermediate result and executes a second part of the fused compound arithmetic operation to produce a final result. In the unchained mode, execution is accomplished by dispatching separate split-execution microinstructions to the first and second instruction execution units. In the chained mode, execution is accomplished by dispatching a single split-execution microinstruction to the first instruction execution unit and sending a chaining control signal or signal group to the second execution unit, causing it to execute its part of the fused arithmetic operation without needing an instruction.

Abstract: A battery measurement device has an input terminal that receives a voltage of a secondary battery, a measurement circuit that measures a voltage value of a voltage received by the input terminal and generates a measurement information signal representing measurement results, a transmission unit that wirelessly transmits the measurement information signal, and a power source circuit that generates a power source voltage having a prescribed voltage value on the basis of the voltage of the input terminal, and supplies the power source voltage to the measurement circuit and the transmission unit.