Patents Assigned to Semiconductor Energy Laboratory Co.
  • Patent number: 11967649
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
  • Patent number: 11967505
    Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Masashi Oota, Yoichi Kurosawa, Noritaka Ishihara
  • Patent number: 11968820
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Yuto Yakubo, Seiya Saito
  • Patent number: 11968889
    Abstract: A light-emitting element having a long lifetime is provided. A light-emitting element exhibiting high emission efficiency in a high luminance region is provided. A light-emitting element includes a light-emitting layer between a pair of electrodes. The light-emitting layer contains a first organic compound, a second organic compound, and a phosphorescent compound. The first organic compound is represented by a general formula (GO). The molecular weight of the first organic compound is greater than or equal to 500 and less than or equal to 2000. The second organic compound is a compound having an electron-transport property. In the general formula (GO), Ar1 and Ar2 each independently represent a fluorenyl group, a spirofluorenyl group, or a biphenyl group, and Ar3 represents a substituent including a carbazole skeleton.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takao Hamada, Hiromi Seo, Kanta Abe, Kyoko Takeda, Satoshi Seo
  • Publication number: 20240130229
    Abstract: A novel high molecular compound is provided. The high molecular compound includes a repeating unit. The repeating unit has a fluorenediyl group, a hole-transport skeleton, and an electron-transport skeleton. The hole-transport skeleton is bonded to the fluorenediyl group through a substituted or unsubstituted first arylene group. The electron-transport skeleton is bonded to the fluorenediyl group through a substituted or unsubstituted second arylene group. In an excited state, intramolecular charge transfer occurs between the hole-transport skeleton and the electron-transport skeleton.
    Type: Application
    Filed: September 18, 2023
    Publication date: April 18, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryo Narukawa, Akira Nagasaka, Kunihiko Suzuki, Hideko Yoshizumi
  • Publication number: 20240124477
    Abstract: A novel organic compound is provided. Alternatively, an organic compound that exhibits light emission with favorable chromaticity is provided. Alternatively, an organic compound that exhibits blue light emission with favorable chromaticity is provided. Alternatively, an organic compound with favorable emission efficiency is provided. Alternatively, an organic compound having a high carrier-transport property is provided. Alternatively, an organic compound with favorable reliability is provided. An organic compound including at least one amino group in which any one of a substituted or unsubstituted dibenzofuranyl group, a substituted or unsubstituted dibenzothiophenyl group, and a substituted or unsubstituted carbazolyl group is boneded to any one of a substituted or unsubstituted naphthobisbenzofuran skeleton, a substituted or unsubstituted naphthobisbenzothiophene skeleton, and a substituted or unsubstituted naphthobenzofuranobenzothiophene skeleton is provided.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 18, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kyoko Takeda, Harue Osaka, Satoshi Seo, Tsunenori Suzuki, Naoaki Hashimoto, Yusuke Takita
  • Publication number: 20240130228
    Abstract: A light-emitting device with high heat resistance in a manufacturing process is to be provided.
    Type: Application
    Filed: January 31, 2022
    Publication date: April 18, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yui Yoshiyasu, Naoaki HASHIMOTO, Tatsuyoshi TAKAHASHI, Sachiko KAWAKAMI, Satoshi SEO
  • Patent number: 11963374
    Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 11963343
    Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Ryunosuke Honda, Tomoaki Atsumi
  • Patent number: 11960174
    Abstract: A pixel electrode or a common electrode is a light-transmissive conductive film; therefore, it is formed of ITO conventionally. Accordingly, the number of manufacturing steps and masks, and manufacturing cost have been increased. An object of the present invention is to provide a semiconductor device, a liquid crystal display device, and an electronic appliance each having a wide viewing angle, less numbers of manufacturing steps and masks, and low manufacturing cost compared with a conventional device. A semiconductor layer of a transistor, a pixel electrode, and a common electrode of a liquid crystal element are formed in the same step.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11961916
    Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Kiyoshi Kato, Tomoaki Atsumi, Shunpei Yamazaki
  • Patent number: 11963360
    Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tomoaki Atsumi, Yuta Endo
  • Patent number: 11961842
    Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 11961871
    Abstract: A display device with high resolution is provided. Manufacturing cost of a display device using a micro LED as a display element is reduced. The display device includes a substrate, a plurality of transistors, and a plurality of light-emitting diodes. The plurality of light-emitting diodes are provided in a matrix over the substrate. Each of the plurality of transistors are electrically connected to at least one of the plurality of light-emitting diodes. The plurality of light-emitting diodes are positioned closer to the substrate than the plurality of transistors are. The plurality of light-emitting diodes emit light to the opposite side of the substrate.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Kusunoki, Shingo Eguchi, Yosuke Tsukamoto, Kazunori Watanabe, Kouhei Toyotaka
  • Patent number: 11963430
    Abstract: An object is to provide a highly reliable display unit having a function of sensing light. The display unit includes a light-receiving device and a light-emitting device. The light-receiving device includes an active layer between a pair of electrodes. The light-emitting device includes a hole-injection layer, a light-emitting layer, and an electron-transport layer between a pair of electrodes. The light-receiving device and the light-emitting device share one of the electrodes, and may further share another common layer between the pair of electrodes. The hole-injection layer is in contact with an anode and contains a first compound and a second compound. The electron-transport property of the electron-transport layer is low; hence, the light-emitting layer is less likely to have excess electrons. Here, the first compound is the material having a property of accepting electrons from the second compound.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taisuke Kamada, Ryo Hatsumi, Daisuke Kubota, Naoaki Hashimoto, Tsunenori Suzuki, Harue Osaka, Satoshi Seo
  • Patent number: 11961994
    Abstract: To provide graphene oxide that has high dispersibility and is easily reduced. To provide graphene with high electron conductivity. To provide a storage battery electrode including an active material layer with high electric conductivity and a manufacturing method thereof. To provide a storage battery with increased discharge capacity. A method for manufacturing a storage battery electrode that is to be provided includes a step of dispersing graphene oxide into a solution containing alcohol or acid, a step of heating the graphene oxide dispersed into the solution, and a step or reducing the graphene oxide.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Ikenuma, Yumiko Yoneda
  • Patent number: 11961979
    Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided. The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Munehiro Kozuma, Takanori Matsuzaki, Ryota Tajima, Shunpei Yamazaki
  • Patent number: 11959165
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Patent number: 11962013
    Abstract: The positive electrode active material layer includes a plurality of particles of a positive electrode active material and a reaction mixture where reduced graphene oxide is bonded to a polymer having a functional group as a side chain. The reduced graphene oxide has a sheet-like shape and high conductivity and thus functions as a conductive additive by being in contact with the plurality of particles of the positive electrode active material. The reaction mixture serves as an excellent binder since the reduced graphene oxide is bonded to the polymer. Therefore, even a small amount of the reaction mixture where the reduced graphene oxide is covalently bonded to the polymer excellently serves as a conductive additive and a binder.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaki Yamakaji, Kuniharu Nomoto
  • Patent number: 11961894
    Abstract: A semiconductor device includes a semiconductor layer over a substrate; a gate insulating film covering the semiconductor layer; a gate wiring including a gate electrode, which is provided over the gate insulating film and is formed by stacking a first conductive layer and a second conductive layer; an insulating film covering the semiconductor layer and the gate wiring including the gate electrode; and a source wiring including a source electrode, which is provided over the insulating film, is electrically connected to the semiconductor layer, and is formed by stacking a third conductive layer and a fourth conductive layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. The source electrode is formed using the third conductive layer. The source wiring is formed using the third conductive layer and the fourth conductive layer.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura