Abstract: A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

Abstract: A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

Abstract: A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

Abstract: A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

Abstract: A hierarchical unary/thermometer coder comprises a cascade of lower level coders that minimize clock loading and clock transitions by only enabling the clocking of a circuit when that circuit is required to change state, thereby minimizing power consumption. At the lowest level, a stage-1 circuit produces a two-bit unary/thermometer code using two NAND gates, an inverter, and a single set-reset latch. An output of the latch forms a least significant bit (LSB) and is used to control transitions of the next most significant bit. A stage-2 circuit produces a four-bit unary/thermometer code using two stage-1 circuits and a NOR gate. A stage-3 circuit produces an eight-bit unary/thermometer code using two stage-2 circuits and a NAND gate. The circuit associated with each higher order bit is only enabled when the next lower bit has been set. Outputs are also provided for generating a “running one” or “running zero” code.

Abstract: A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting.

Abstract: A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting.

Abstract: An anti-jamming system includes a tunable negative jamming signal feedback loop for feedback suppression of a received jamming signal. The system includes a zero IF phase locked loop (PLL) jamming signal receiver having a synchronous demodulator and a phase detector. A VCO is included in the PLL, as well as a phase detector and a loop filter. A replica jamming signal generator includes a tracking modulator with a baseband signal input coupled to an output of a synchronous demodulator in the receiver and a carrier input provided by the VCO. An output of the tracking modulator is negatively fed back to the input of the receiver to suppress the jamming signal in the received input.

Abstract: FM receiver including an RF input circuit followed by a tunable mixer stage for frequency conversion of an RF FM signal into an IF FM signal, which is coupled to an FM input of a first narrow-band IF filter. The center frequency of the first narrow-band IF filter is controlled to vary in dependence on the IF FM signal. The first narrow-band IF filter is subsequently coupled to a first FM demodulator and a first LF signal processing unit. To increase the receiver's selectivity and sensitivity without adversely affecting tracking stability, the FM input of a first narrow-band IF filter is coupled through a second FM demodulator to a control input of said first narrow-band FM tracking filter for a feed forward tracking control of the center frequency of said first narrow-band FM tracking filter with the momentary frequency of the IF FM signal.

Abstract: Method for reducing noise included in a stereo reproduction signal derived from a stereo input signal characterized by the steps of: *varying stereo channel separation of said stereo reproduction signal with frequency within the frequency range of the stereo input signal in accordance with the frequency response of a filter selectivity located around a center frequency to obtain a stereo channel separation peak value at said center frequency; *at a continuing increase of said noise, decreasing the bandwidth of said filter selectivity to a pre-determined non-zero bandwidth while maintaining the channel separation within the bandwidth of said filter selectivity substantially at said channel separation peak value.

Abstract: Method and mixer using the method for mixing a complex digital input vector with an oscillator reference signal based on a separation of the mixing process in mainly two processing steps, to with a first step in which a set of n real part values Vi, is derived from said complex digital input vector in which n is an integer larger than 1 and in which each real part value Vi is proportional to the real part of the digital input vector when being rotated over predetermined phase angles ?i=?0+i*??, respectively, for a constant ?0, ?? corresponding to either 2?/n or ?2?/n, with integer i varying between 0 and n?1 and a second step, in which said n real part values and Vi are each consecutively selected to be coupled to a load.

Abstract: Anti jamming system comprising a tunable negative jamming signal feedback loop for feedback suppression of a received jamming signal, including a receiver receiving an jamming signal followed by a jamming signal replica generator for generating an replica jamming signal. The receiver comprising a zero IF PLL jamming signal receiver having a synchronous demodulator and a phase detector, signal inputs thereof being coupled to said input means and carrier inputs coupled to in-phase and phase quadrature oscillator outputs, respectively, of a local voltage controlled oscillator (VCO), said VCO receiving a tuning control signal for tuning the zero IF PLL jamming signal receiver at the carrier frequency of the jamming signal. The VCO is included in a phase locked loop (PLL) comprising subsequent to the VCO, said phase detector and a loop filter.

Abstract: Anti jamming system comprising a tunable negative jamming signal feedback loop for feedback suppression of a received jamming signal, including an receiver receiving an jamming signal followed by a replica jamming signal generator for generating an replica jamming signal. The receiver comprising a zero IF PLL receiver having a synchronous demodulator and a phase detector, signal inputs thereof being coupled to said input means and carrier inputs coupled to in-phase and phase quadrature oscillator outputs, respectively, of a local voltage controlled oscillator (VCO), said VCO receiving a tuning control signal for tuning the zero IF PLL receiver at the carrier frequency of the jamming signal. The VCO is included in a phase locked loop (PLL) comprising subsequent to the VCO, said phase detector and a loop filter.

Abstract: Controllable operational transconductance power amplifier (controllable power OTA) including an input stage receiving a differential input signal (Ovin) and deriving therefrom first (i1) and second (i2) low power current signals being coupled to first (ccs1) and second (ccs2) current controlled output current sources being arranged in class B push pull configuration. To obtain an effective gain control while securing power efficiency and linearity, the overall gain of the power OTA is controlled by varying the gain or transconductance of the input stage (c15) and by the use of means for bi-directionally rectifying said first (i1) and second (io) low power current signals and providing in mutual alternation power amplification of said first (i1) and second (i2) low power current signals into first (I01) and second (Io2) mutually exclusive high power current output signals, which are supplied through a current summer to a current output (I0) of said linear power amplifier.

Abstract: An integrated RC filter comprises a first resistor being coupled to a first capacitor through a first node and a signal input of said integrated RC filter is coupled through one of the first resistor and the first capacitor to the first node. To allow for an increase in the RC time constant of the RC filter without losing signal transparency, amplification means are included between said signal input and said one of the first resistor and the first capacitor having a gain factor substantially larger than unity, said first node being coupled through attenuation means to a signal output, said attenuation means having an attenuation factor substantially.

Abstract: Multiplier device comprising first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS1 to MSn with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of said multiplier device according to the invention, n is greater than 2, outputs of said multipliers M1 to Mn are respectively coupled through weighting circuits W1 to Wn with respective fixed weighting factors WF1 to WFn to an adder circuit, said mixing signals MS1 to MSn having respective phase angles ?i corresponding to ?i=i*??, said weighting factors WFi corresponding to the sine value of said respective phase angles ?i=i*?? with ?? being the mutual phase difference between each two phase consecutive mixing signals corresponding to ?/(n+1) and i varying from 1 to n.

Abstract: Tunable low noise amplifier using an RF current feed back loop (L) coupled between input (IM) and output (OM) means and including first (CAI) and second (CA2) serially coupled first order lowpass RF current amplifiers as well RF current inverter means (INV). To obtain narrow bandpass selectivity within a relatively wide tuning range e.g. from 40 MHz to 1000 MHz said first RF current amplifier is being provided with a current gain larger than that of the second RF current amplifier, and a 3 dB cut off frequency lower than the 3 dB cut off frequency of said second RF current amplifier, a tuning control signal being supplied to both first and second RF current amplifiers to vary the respective 3 dB cut off frequencies thereof.

Abstract: Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers (OTAs), having a controllable transconductance Gm from a differential voltage input having first and second differential voltage input terminals to a single current output carrying a single phase current output signals, said first and second OTAs being provided with first and second control inputs, respectively, said filter input being coupled to the first differential voltage input terminal of said first OTA.

Abstract: Controllable operational transconductance power amplifier (controllable power OTA) including an input stage receiving a differential input signal (OVin) and deriving therefrom first (i1) and second (i2) low power current signals being coupled to first (ccs1) and second (ccs2) current controlled output current sources being arranged in class B push pull configuration. To obtain an effective gain control while securing power efficiency and linearity, the overall gain of the power OTA is controlled by varying the gain or transconductance of the input stage (c15) and by the use of means for bi-directionally rectifying said first (i1) and second (io) low power current signals and providing in mutual alternation power amplification of said first (i1) and second (i2) low power current signals into first (I01) and second (Io2) mutually exclusive high power current output signals, which are supplied through a current summer to a current output (I0) of said linear power amplifier.

Abstract: Receiver comprising an RF input filter including a digitally controlled capacitor bank with n capacitors being controlled by a tuning control signal for varying the tuning frequency of the RF input filter within a tuning range. For an improvement of the receiver in price/performance ratio the n capacitors of the digitally controlled capacitor bank are monolythically integrated, whereas the bandwidth of the tunable RF input filter is being adjusted to the maximum relative spread of said capacitors. A continuous tuning control signal is being supplied through an analogue to digital (AD) converter to said capacitor bank and to a first input of a differential stage, an output of the AD converter being coupled through a digital to analogue (DA) converter to a second input of a differential stage, an output of the differential stage being coupled to a control terminal of a variable capacitance diode being arranged in parallel to the digitally controlled capacitor bank.