Abstract: The present disclosure teaches a photolithography plate and a mask correction method, and relates to the field of semiconductor technologies. In forms of the mask correction method, a patterned mask is formed on a substrate, a location of a scattering bar embedded in the substrate is determined according to the mask, and an opening is formed at the determined location so as to embed the scattering bar in the opening. A scattering bar is embedded in a substrate of a photolithography plate so as to effectively avoid the impact of the scattering bar on a mask pattern, reduce a deposition loss, improve the correction effect, and shorten a correction time.

Abstract: A semiconductor structure and a method for forming same are provided. The forming method includes: providing a substrate, a fin protruding from the substrate, and at least two channel laminates sequentially located on the fin, where each channel laminate includes a sacrificial layer and a channel layer; forming a gate structure across the channel laminates; forming, in the channel laminates, a groove that exposes the fin, where after the groove is formed, the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer encircle a first trench, adjacent channel layers and the remaining sacrificial layer between the adjacent channel layers encircle a second trench; forming first spacers in the first trench and the second trench; and forming a source-drain doping layer in the groove.

Abstract: The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed.

Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base the dummy gate structure exposes, and the interlayer dielectric layer exposes the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, where the isolation structure further extends into the base; after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, where the gate electrode material further covers the top of the interlayer dielectric layer; and performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, where the step of the

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A semiconductor structure and a method for forming same are provided. One form of the method includes: providing a substrate including a device unit area, where at least two fins are formed on the substrate, a channel structure layer is formed on the fins, which includes a first channel structure layer located on at least one fin, a second channel structure layer located on at least one fin, and a third channel structure layer located on at least one fin, the first channel structure layer includes multiple channel laminates, each channel laminate includes a first sacrificial layer and a first channel layer; forming a dummy gate structure across the channel structure layer; forming a source-drain doping layer on two sides of the dummy gate structure; and forming a gate structure at positions of the dummy gate structure and the first sacrificial layer.

Abstract: The present disclosure provides a semiconductor structure forming method, including: providing a base, a first mask layer and a second mask layer located at the top of the first mask layer being formed on the base, and the second mask layer internally having a first opening, a second opening and a third opening; forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening; forming a first pattern layer filling the first opening, the second opening and the third opening, the first pattern layer internally having a first groove; etching to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; and by using the second mask layer and the first side wall layers as masks, etching the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as

Abstract: Disclosed are a semiconductor structure and a method for forming same.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate; forming a source and a drain that are at least partially located in the substrate; forming a diffused layer on a surface of at least one of the source or the drain, where a conductivity type of the diffused layer is the same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain; and performing an annealing processing after the diffused layer is formed. The present disclosure can increase a doping density at a surface of a source and/or a drain, helping to reduce a contact resistance, thereby improving performance of a device.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate.

Abstract: This disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing semiconductor FinFET devices. The method particularly includes pre-removal of a predetermined thickness of a first region of an isolation region on sides of a fin that is not covered by a pseudo gate such that when a layer of second region of the isolation region covered by the pseudo gate is sacrificially removed during a removal of the pseudo gate, the upper surfaces of the remaining first region and the remaining second region of the isolation region are approximately leveled. By using such a method, DC and AC performances of a resulting FinFET device is improved.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.

Abstract: The present disclosure provides implementations of a level shifter (LS), an integrated circuit, and a method. A LS may run in a first mode and a second mode, alternating with each other.

Abstract: A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins.

Abstract: The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.

Abstract: The present disclosure provides methods and apparatus for designing an interconnection structure and methods for manufacturing an interconnection structure, and relates to the technical field of semiconductors. An implementation of the method may include: designing n virtual interconnection units according to a number of metal interconnection layers in a circuit area of a chip design drawing, where an ith virtual interconnection unit includes i metal interconnection layers, and where adjacent metal interconnection layers in a jth virtual interconnection unit are connected by using vias, and n?2, 1?i?n, and 2?j?n; and filling an area in the chip design drawing outside the circuit area with virtual interconnection units, where the jth virtual interconnection unit is filled, and a (j?1)th virtual interconnection unit is not filled unless there is no space in the area for the jth virtual interconnection unit.

Abstract: The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same.

Abstract: This disclosure relates to a semiconductor structure for, e.g., a high-k metal gate fin field-effect transistor, and a manufacturing method therefor. The method may include providing a substrate structure including a first portion for forming a first PMOS device and a second portion for forming a second PMOS device; forming a first P-type work function adjustment layer on the substrate structure; forming a protective layer on the first P-type work function adjustment layer; patterning the protective layer to expose the first P-type work function adjustment layer on the first portion; oxidizing the exposed first P-type work function adjustment layer on the first portion; removing the protective layer; and forming a second P-type work function adjustment layer on the first P-type work function adjustment layer.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, a dummy gate structure being formed on the base, a source/drain doping region being formed in the base on both sides of the dummy gate structure, a dielectric layer being formed on the base exposed by the dummy gate structure, and the dielectric layer covering the source/drain doping region; etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region; forming a contact plug in the contact hole, the contact plug being electrically connected to the source/drain doping region; after forming the contact plug, removing the dummy gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening. Embodiments of the present disclosure are advantageous to simplify process complexity and increase process windows.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.