Patents Assigned to Semiconductor Manufacturing Company
  • Package and method of manufacturing the same
    Patent number: 11749607
    Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.
    Type: Grant
    Filed: March 27, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Chen-Hua Yu, Kuo-Chung Yee, Szu-Wei Lu, Ying-Ching Shih
  • Method of testing a memory circuit and memory circuit
    Patent number: 11749370
    Abstract: A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-I Wu, Shih-Lien Linus Lu, Sai-Hooi Yeong
  • Fin field-effect transistor and method of forming the same
    Patent number: 11749681
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J. H. Wang
  • Transparent refraction structure for an image sensor and methods of forming the same
    Patent number: 11749700
    Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substrate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Shiang Lin, Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Integrated circuit with constrained metal line arrangement
    Patent number: 11748550
    Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: September 5, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: XinYong Wang, Qiquan Wang, Li-Chun Tien, Yuan Ma
  • Static random access memory with magnetic tunnel junction cells
    Patent number: 11751375
    Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ping-Wei Wang, Jui-Lin Chen, Yu-Kuan Lin
  • Decoupling FinFET capacitors
    Patent number: 11749759
    Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Source/drain features
    Patent number: 11749719
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ruei-Ping Lin, Kai-Di Tzeng, Chen-Ming Lee, Wei-Yang Lee
  • Systems and methods for integrated circuit layout
    Patent number: 11748542
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
  • Package structure
    Patent number: 11749582
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Wafer-level packaging of solid-state biosensor, microfluidics, and through-silicon via
    Patent number: 11747298
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang
  • Method for non-destructive inspection of cell etch redeposition
    Patent number: 11749569
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Doping profile for strained source/drain region
    Patent number: 11749752
    Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Semiconductor memory devices and methods of manufacturing thereof
    Patent number: 11749623
    Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chia-En Huang
  • Memory circuits
    Patent number: 11749664
    Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Ching Liu, Yih Wang, Chia-En Huang
  • EUV vessel perimeter flow auto adjustment
    Patent number: 11747735
    Abstract: In a method of generating extreme ultraviolet (EUV) radiation in a semiconductor manufacturing system one or more streams of a gas is directed, through one or more gas outlets mounted over a rim of a collector mirror of an EUV radiation source, to generate a flow of the gas over a surface of the collector mirror. The one or more flow rates of the one or more streams of the gas are adjusted to reduce an amount of metal debris deposited on the surface of the collector mirror.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Chang Hsu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Ruthenium oxide film and ruthenium liner for low-resistance copper interconnects in a device
    Patent number: 11749604
    Abstract: Selective ruthenium and selective ruthenium oxide may be used in single damascene processes and/or dual damascene processes to form BEOL metallization layers and vias of an electronic device. A selective ruthenium liner may be formed to achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shu-Cheng Chin
  • Transport system, associated movable container and method
    Patent number: 11749548
    Abstract: A transport system, including: a sensor, a controller and a power panel. The sensor determines a zone and sends a quantity information in response to a quantity of vehicles in the zone. The controller is arranged to send an output signal in accordance with the quantity information. The power panel is arranged to output a current in accordance with the output signal for driving vehicles in the zone, wherein the current is outputted to a cable extending through the zone.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Hsien Li, Chi-Feng Tung, Hsiang Yin Shen
  • Integrated devices in semiconductor packages and methods of forming same
    Patent number: 11749626
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • Multi-stage bit line pre-charge
    Patent number: 11749321
    Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan, Yen-Huei Chen