Patents Assigned to Semiconductor Manufacturing Company
  • Alignment mark design for packages
    Patent number: 11742298
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu
  • Interface of integrated circuit die and method for arranging interface thereof
    Patent number: 11742295
    Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 29, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Igor Elkanovich, Amnon Parnass, Chia-Hsiang Chang, Tsai-Ming Yang, Yen-Chung T. Chen, Ting-Hsu Chien, Yuan-Hung Lin, Chao-Ching Huang, Li-Ya Tseng, Pei Yu, Jia-Liang Chen, Yen-Wei Chen, Chung-Kai Wang, Chun-Hsu Chen, Yu-Ju Chang, Li-Hua Lin, Zanyu Yang
  • Structure and method for enhancing robustness of ESD device
    Patent number: 11742236
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Mechanism for FinFET well doping
    Patent number: 11742237
    Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
  • Methods and apparatus of charge-sharing locking with digital controlled oscillators
    Patent number: 11742865
    Abstract: An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Wen-Yuan Tsai, Chih-Hsien Chang
  • Memory device comprising source line coupled to multiple memory cells and method of operation
    Patent number: 11742024
    Abstract: A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Cheng-Hsiung Kuo, Chung-Chieh Chen
  • Fingerprint sensor in info structure and formation method
    Patent number: 11741737
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • Routing-resource-improving method of generating layout diagram, system for same and semiconductor device
    Patent number: 11741288
    Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Wei-Cheng Lin, Jay Yang
  • Mask cleaning
    Patent number: 11740563
    Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
  • Method of filling gaps with carbon and nitrogen doped film
    Patent number: 11742201
    Abstract: A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Lithography apparatus and method using the same
    Patent number: 11740564
    Abstract: A method comprises loading a wafer onto a wafer chuck of a lithography apparatus, projecting an extreme ultraviolet light through an opening of a frame structure of the lithography apparatus, onto the wafer, and introducing an airflow from an air curtain module on the wafer chuck toward the frame structure, wherein the air curtain module surrounds the wafer. The airflow forms an air curtain around the wafer, and shields the wafer from contaminants from the frame structure or a wafer stage.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao-Hsin Chen, Chia-Yu Lee
  • Integrated fan-out package having stress release structure
    Patent number: 11742322
    Abstract: A semiconductor package includes a redistribution structure, a first die, a second die and a buffer layer. The second die is disposed between the first die and the redistribution structure, and the second die is electrically connected to the first die and bonded to the redistribution structure. The buffer layer is disposed on a first sidewall of the second die, wherein a second sidewall of the buffer layer is substantially flush with a third sidewall of the first die.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Po-Chen Lai, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain
    Patent number: 11742399
    Abstract: A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yang Ho, Tsai-Jung Ho, Jr-Hung Li, Tze-Liang Lee
  • Semiconductor devices and method of forming the same
    Patent number: 11744084
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, an interconnect structure, a memory cell and a conductive via. The semiconductor substrate has a first side and a second side opposite to the first side. The gate structure is disposed over the first side of the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate aside the gate structure. The interconnect structure is disposed over the first side of the semiconductor substrate and electrically connected to the source region. The memory cell is disposed over the second side of the semiconductor substrate and electrically connected to the drain region. The conductive via is disposed in the semiconductor substrate between the drain region and the memory cell and electrically connects the drain region and the memory cell.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku Shen, Liang-Wei Wang, Dian-Hau Chen, Yen-Ming Chen
  • Semiconductor device including back side power supply circuit
    Patent number: 11742285
    Abstract: A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gerben Doornbos, Marcus Johannes Henricus Van Dal
  • Memory device
    Patent number: 11744060
    Abstract: A memory device is provided. The memory device includes a plurality of memory cells. Each memory cell includes a latch circuit formed of N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The NFETs are formed at a surface of a semiconductor substrate, and the PFETs are disposed at an elevated level over the NFETs.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huai-Ying Huang, Yu-Ming Lin
  • Process including a re-etching process for forming a semiconductor structure
    Patent number: 11742317
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Pogo pin-free testing device for IC chip test and testing method of IC chip
    Patent number: 11740260
    Abstract: A pogo pin-free testing device for IC chip test includes a load board, a ceramic interposer disposed on the load board, and copper core balls. The ceramic interposer has first and second surfaces and connecting points, and the second surface of the ceramic interposer faces the load board. Each connecting point has through holes penetrating the first and second surfaces, and an inner sidewall surface thereof has a metallization layer. The metallization layer is extended to a portion of the first surface and a portion of the second surface. In each of the connecting points, an area of an extending portion of the metallization layer extended to the second surface is less than an area of an extending portion of the metallization layer extended to the first surface. The copper core balls are disposed between the load board and the through holes of each connecting point of the ceramic interposer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: August 29, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng, Pei-Shiou Huang
  • Semiconductor device including a plurality of dielectric materials between semiconductor dies and methods of forming the same
    Patent number: 11742325
    Abstract: A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Tzu-Chung Tsai
  • Method and system for generating layout diagram of semiconductor device including waveguide heater and method of forming same
    Patent number: 11740492
    Abstract: A method of forming semiconductor device includes forming an active layer in a substrate including forming components of one or more transistors; forming an MD and gate (MDG) layer over the active layer including forming a gate line; forming a metal-to-S/D (MD) contact structure; and forming a waveguide between the gate line and the MD contact structure; forming a first interconnection layer over the MDG layer including forming a first via contact structure over the gate line; forming a second via contact structure over the MD contact structure; and forming a heater between the first and second via contact structures and over the waveguide.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho