Patents Assigned to Semiconductor Manufacturing International (Beijing) Corporation
  • Patent number: 11004752
    Abstract: A fin field-effect transistor (fin-FET) includes a substrate having a plurality of discrete fin structures thereon; a chemical oxide layer on at least a sidewall of a fin structure; a doped layer containing doping ions on the chemical oxide layer; and a doped region in the fin structure containing doping ions diffused from the doping ions in the doped layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: May 11, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Publication number: 20210134659
    Abstract: A semiconductor structure and a forming method thereof are provided.
    Type: Application
    Filed: April 30, 2020
    Publication date: May 6, 2021
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wang WEI, Su BO, Hu You CUN
  • Patent number: 10985276
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 20, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Meng Zhao
  • Patent number: 10983160
    Abstract: Circuits and methods for measuring a working current of a circuit module. An exemplary circuit for measuring a working current of a circuit module includes a capacitor. The capacitor supplies a voltage to the circuit module using a voltage on the two terminals of the capacitor. The circuit also includes a voltage measuring module. The voltage measuring module measures a voltage change amount on the two terminals of the capacitor in an unit time. The working current of the circuit module is determined by the circuit according to the voltage change amount on the two terminals of the capacitor in the unit time and a capacitance of the capacitor.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 20, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Chia Chi Yang, Zhi Bing Deng, Teng Ye Wang, Wen Jun Weng
  • Patent number: 10978575
    Abstract: A semiconductor structure is provided and includes a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer; and a gate electrode layer on the gate barrier layer structure. The dielectric barrier layer structure is doped with silicon and the gate barrier layer structure is doped with silicon.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hao Deng
  • Patent number: 10978577
    Abstract: A method for fabricating a semiconductor structure includes forming a fin structure and a gate structure; and forming a source/drain trench in the fin structure on each side of the gate structure. The source/drain trench includes a bottom region and a top region located above the bottom region. Along an extension direction of the fin structure, the dimension of the top region of the source/drain trench is larger than the dimension of the bottom region of the source/drain trench. Along the extension direction of the fin structure, the shortest distance from a sidewall surface of the top region of the source/drain trench to a sidewall surface of the gate structure is smaller than the shortest distance from a sidewall surface of the bottom region of the source/drain trench to the sidewall surface of the gate structure. The method further includes forming a source/drain doped layer in the source/drain trench.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10978349
    Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes forming a first type of fin sidewall spacers and a second type of fin sidewall spacers. The first type of fin sidewall spacers are formed on two sidewall surfaces of a third fin portion group along a width direction of the third fin portions and two sidewall surfaces of a fourth fin portion group along a width direction of the fourth fin portions. The second type of fin sidewall spacers are formed between adjacent third fin portions and sidewall surfaces of the third fin portions and between adjacent fourth fin portions and on sidewall surfaces of the fourth fin portions. Top surfaces of the first type of fin sidewall spacers are higher than top surfaces of the second type of fin sidewall spacers and top surfaces of the third fin portions and the fourth fin portions.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Poren Tang
  • Patent number: 10971367
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhaoxu Shen, Duohui Bei
  • Patent number: 10971405
    Abstract: A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 10964600
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, including isolation regions and a device region between adjacent isolation regions; a plurality of fin structures, formed on the device region of the substrate; and an isolation layer, formed on the substrate. A top surface of the isolation layer is lower than top surfaces of the fin structures. A height of each fin structure exposed by the isolation layer is identical.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10957700
    Abstract: A semiconductor device and a fabrication method are provided. The method includes: providing a base substrate; forming a first gate structure and doped source/drain layers on the base substrate; forming a dielectric layer on a surface of the base substrate; forming a first trench on the doped source/drain layers through the dielectric layer, where the first trench includes a first region and a second region under the first region, and an angle between a sidewall of the first region and the surface of the base substrate is a first angle; forming a first conductive structure in the second region of the first trench; after forming the first conductive structure, forming an insulation layer in the first region of the first trench; forming a recess, exposing the first gate structure, in the dielectric layer using the insulation layer as a mask; and forming a second conductive structure in the recess.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 23, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Publication number: 20210083093
    Abstract: The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 18, 2021
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng ZHAO
  • Patent number: 10950525
    Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 16, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Patent number: 10944004
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming a first stress layer in the base substrate. The method also includes forming a gate structure on the base substrate. The first stress layer in the base substrate is on both sides of the gate structure. In addition, the method includes after forming the gate structure, forming an opening in the first stress layer by back-etching the first stress layer. Further, the method includes forming a second stress layer in the opening of the first stress layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 9, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10943912
    Abstract: A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 9, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Publication number: 20210066326
    Abstract: A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer.
    Type: Application
    Filed: March 13, 2020
    Publication date: March 4, 2021
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Han LIANG, Wang Hai YING
  • Patent number: 10937896
    Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Yan Wang
  • Patent number: 10937692
    Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 2, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jiquan Liu
  • Publication number: 20210057542
    Abstract: A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan WANG
  • Patent number: 10930785
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a first dielectric layer on the base substrate; a target gate structure in the first dielectric layer and on the base substrate. The target gate structure includes a target structure body and a target spacer wall on sidewalls of the target gate structure body. The semiconductor device further includes a protective layer on a top surface of the target gate structure, in the first dielectric layer. The semiconductor device further includes conductive plugs in the first dielectric layer on sides of the target gate structure and the protective layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 23, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li