Patents Assigned to Semiconductor Manufacturing International (Beijing) Corporation
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Publication number: 20230223452Abstract: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.Type: ApplicationFiled: March 21, 2023Publication date: July 13, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Bo Su, Hansu OH, Chunsheng ZHENG, Erhu ZHENG, Haiyang ZHANG
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Publication number: 20230215927Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.Type: ApplicationFiled: March 10, 2023Publication date: July 6, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Jisong JIN, Subhash KUCHANURI, Abraham YOO
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Patent number: 11695035Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate and a dummy gate structure on the substrate. The substrate contains source-drain openings on both sides of the dummy gate structure. The semiconductor structure also includes a first stress layer formed on a sidewall of a source-drain opening of the source-drain openings. Further, the semiconductor structure includes a second stress layer formed at a bottom of the source-drain opening and on the first stress layer. The second stress layer fully fills the source-drain opening, and stress of the first stress layer is less than stress of the second stress layer.Type: GrantFiled: March 25, 2021Date of Patent: July 4, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Meng Zhao
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Patent number: 11695062Abstract: A semiconductor structure and a forming method thereof are provided.Type: GrantFiled: April 30, 2021Date of Patent: July 4, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Zheng Erhu, Ye Yizhou, Zhang Gaoying
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Publication number: 20230207303Abstract: The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.Type: ApplicationFiled: December 20, 2022Publication date: June 29, 2023Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Qingzhao LIU, Rex YAN, Yajun ZHAO, Elegant LIU, Yang WANG
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Patent number: 11688798Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.Type: GrantFiled: April 1, 2021Date of Patent: June 27, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Xiang Hu
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Patent number: 11682725Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a first well region and a second well region in the base substrate; a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate; a dielectric layer on the base substrate; and an isolation layer in the dielectric layer. The dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure. The isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.Type: GrantFiled: October 7, 2021Date of Patent: June 20, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fei Zhou
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Patent number: 11682586Abstract: A semiconductor structure is provided. The semiconductor structure includes: a base substrate having an opening; and a first gate layer formed in the opening. In the first gate layer closes a top of the opening and the first gate layer includes at least one void. The semiconductor structure further includes a second gate layer formed on the first gate layer. An atomic radius of the material of the second gate layer is smaller than gaps among atoms of the material of the first gate layer and the void is filled by atoms of one of the material of the first gate layer and the material of the second gate layer.Type: GrantFiled: December 14, 2021Date of Patent: June 20, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Jian Qiang Liu, Chao Tian, Zi Rui Liu, Ching Yun Chang, Ai Ji Wang
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Patent number: 11676865Abstract: Semiconductor structures and fabrication methods thereof are provided. The method includes providing a substrate; forming a stacked material structure on the substrate; and forming trenches in the stacked material structure. Bottoms of the trenches are in the first material layer, the trenches are arranged along a first direction and form an initial stacked structure sequentially including an initial first layer, an initial second layer and an initial third layer. The method also includes etching the initial third layer to form transitional third layers arranged along a second direction perpendicular to the first direction; removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure including a first layer, a second layer and the transitional third layers; and forming a gate structure.Type: GrantFiled: April 29, 2021Date of Patent: June 13, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Haiyang Zhang, Zhenyang Zhao, Enning Zhang
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Patent number: 11664234Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a to-be-etched layer; forming a first sacrificial film on the to-be-etched layer; and forming a plurality of discrete first sidewall spacers and sidewall trenches on the first sacrificial film. Each sidewall trench is located between two adjacent first sidewall spacers; the first sidewall trenches include a first sidewall trench and a second sidewall trench, and a width of the second sidewall trench is greater than that of the first sidewall trench. The method also includes forming a second sidewall spacer in the first sidewall trench to fill the first sidewall trench; and etching the first sacrificial film using the first sidewall spacers and the second sidewall spacer as an etching mask to form a plurality of discrete first sacrificial layers on the to-be-etched layer.Type: GrantFiled: September 25, 2020Date of Patent: May 30, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Jisong Jin
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Patent number: 11664227Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a to-be-etched layer; forming an initial mask layer over the to-be-etched layer; forming a patterned structure, on the initial mask layer and exposing a portion of the initial mask layer; forming a barrier layer on a sidewall surface of the patterned structure; using the patterned structure and the barrier layer as a mask, performing an ion doping process on the initial mask layer to form a doped region and an un-doped region between doped regions in the initial mask layer; removing the patterned structure and the barrier layer; and forming a mask layer on a top surface of the to-be-etched layer by removing the un-doped region. The mask layer includes a first opening exposing the top surface of the to-be-etched layer.Type: GrantFiled: September 17, 2020Date of Patent: May 30, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Qian Jiang Zhang, Bo Su, Tao Dou, Lin Lin Sun
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Patent number: 11665972Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a conductive layer in the substrate and having a surface exposed by the substrate. A groove is formed in the substrate and adjacent to the conductive layer, and a sidewall of the groove exposes a portion of a sidewall surface of the conductive layer. The semiconductor structure also includes a lower electrode layer located in the groove and on a top surface of the conductive layer. The lower electrode layer covers the top surface and the portion of the sidewall surface of the conductive layer.Type: GrantFiled: September 26, 2020Date of Patent: May 30, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Ming Zhou
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Patent number: 11658239Abstract: The present disclosure provides a semiconductor device and a fabrication method. The semiconductor device includes: a substrate; a first well region in the substrate, having first ions; an isolation layer in the first well region; a second well region and a third well region, formed in the first well region, located respectively on opposite sides of the isolation layer, having second ions with an opposite conductivity type as the first ions, and with a minimum distance from the isolation layer greater than zero; a first gate structure on the second well region and the first well region; a second gate structure on the third well region and the first well region; a barrier gate on the isolation layer, located between the first gate structure and the second gate structure, and having the second ions; and source-drain doped layers in the second well region and the third well region, respectively.Type: GrantFiled: January 10, 2020Date of Patent: May 23, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Xuemei Wang, Fugang Chen, Yun Xue
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Patent number: 11658228Abstract: A method for manufacturing semiconductor devices is provided. The method includes: providing a substrate structure comprising a semiconductor substrate and a trench insulator portion in the semiconductor substrate; forming a dummy gate on the semiconductor substrate; performing a first ion implantation into the semiconductor substrate to form a first doped region between the trench insulator portion and the dummy gate; and forming a first connecting member connecting the dummy gate with the first doped region.Type: GrantFiled: June 9, 2021Date of Patent: May 23, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Gang Qian, Yiming Miao, Yanlin Sun, Xubo Chen
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Patent number: 11658076Abstract: Semiconductor devices are provided. An exemplary semiconductor device includes a semiconductor substrate having a first region. The first region includes a first middle region and a first edge region adjacent to and surrounding the first middle region; and a surface of the first middle region of the semiconductor substrate is higher than a surface of the first edge region of the semiconductor substrate. The semiconductor device also includes a plurality of first fins discretely formed on the first middle region of the semiconductor substrate; and an isolation structure formed on the first middle region of the semiconductor substrate and the first edge region of the semiconductor substrate and covering portions of sidewall surfaces of the first fins.Type: GrantFiled: June 7, 2021Date of Patent: May 23, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fei Zhou
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Patent number: 11658112Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate; a gate structure on the substrate and extending along a first direction; source/drain doped layers in the substrate at sides of the gate structure; a first conductive structure on the source/drain doped layers; an opening at a top of the gate structure and the first conductive structure; and a second conductive structure in the opening. The opening extends along a second direction and the second direction is different from the first direction. The second conductive structure is insulated from the first conductive structure and in contact with the gate structure.Type: GrantFiled: April 2, 2021Date of Patent: May 23, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Nan Wang
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Patent number: 11659710Abstract: A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.Type: GrantFiled: September 22, 2020Date of Patent: May 23, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Liang Han, Hai Ying Wang
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Patent number: 11658067Abstract: A method for forming a semiconductor structure includes providing an initial semiconductor structure formed in a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer to expose a portion of the initial semiconductor structure; etching the portion of the initial semiconductor structure exposed at a bottom of the first opening to form a second opening in the initial semiconductor structure; and forming a contact layer in the second opening and a third opening in the contact layer. The contact layer has a concave top surface, and the third opening is located above the concave top surface of the contact layer and under the first opening. The method further includes forming a conductive structure in the first opening and the third opening.Type: GrantFiled: August 10, 2020Date of Patent: May 23, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Hailong Yu, Jingjing Tan, Hao Zhang
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Patent number: 11651964Abstract: A semiconductor structure and a forming method thereof are provided.Type: GrantFiled: March 31, 2021Date of Patent: May 16, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Jisong Jin
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Patent number: 11646236Abstract: Semiconductor device is provided. The semiconductor device includes a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region. A first work function layer is formed on the base substrate in the second region. A second work function layer is formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.Type: GrantFiled: July 3, 2019Date of Patent: May 9, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Fei Zhou