Abstract: Protection circuit and integrated circuit are provided. A protection circuit includes a discharge passage, configured to perform an electro-static discharge and a controller configured to blow out the electric fuse after the discharge passage fulfills electro-static discharge. The discharge passage includes an electric fuse.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first dielectric layer having a first region and a second regions at each of two sides of the first region on the semiconductor substrate; forming a first opening in the first region of the first dielectric layer and a second opening in each of the second regions of the first dielectric layer; forming a first interconnect member in the first opening; forming a second interconnect member with a top surface lower than a top surface of the first dielectric layer in each of the second openings; forming a second dielectric layer having a third opening with a bottom exposing a top surface of the first interconnect member on surfaces of the first interconnect member, second interconnect members and the first dielectric layer; and forming an interconnect structure in the third opening.

Abstract: In accordance with some embodiments of the present disclosure, a semiconductor structure and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: forming a base substrate; forming a gate structure on the base substrate; forming openings in the base substrate on both sides of the gate structure; forming a barrier layer on sidewalls of the openings adjacent to the gate structure; and forming a doped layer in the openings, and forming a source region or a drain region in the doped layer.

Abstract: Testing structures, and their fabrication methods and testing methods are provided. An exemplary testing structure includes a base substrate containing a well region; a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region; a dielectric layer on the base substrate and covering the well region and the first doped epitaxial region; a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug. The second contact plug and the third contact plug pass through the dielectric layer and electrically connected with the first doped epitaxial region. The second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug.

Abstract: A physical unclonable function (PUF) chip and a fabrication method are provided. The fabrication method includes: forming an array of spaced electrode plates on a top metal connection layer of a nude chip, while forming the top metal connection layer; forming a deposition layer, on the top metal connection layer between adjacent electrode plates; forming openings between adjacent electrode plates in a row, each opening having a circumference tangent to the adjacent electrode plates; coating a conductive coating layer on the nude chip, the conductive coating layer including conductive particles with randomly distributed size; and packaging the nude chip to provide the PUF chip.

Abstract: A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure including a first electrode layer, forming a sacrificial layer on the first electrode layer, the sacrificial layer including a recess having a pointed bottom defining a depth, forming a second electrode layer on the sacrificial layer, the second electrode layer including a first opening exposing the recess, and forming a support layer filling the recess, the first opening, and on the second electrode layer. A portion of the support layer filling the recess forms a stopper having a height equal to the depth of the recess. The method also includes forming a second opening extending through the support layer and the second electrode layer and exposing a surface of the sacrificial layer, and removing a portion of the sacrificial layer to form a cavity.

Abstract: The present disclosure provides semiconductor structures. An exemplary semiconductor structure includes a substrate having a first region and a second region; an isolation structure formed in the substrate in the first region; a compensation doping region formed in the substrate in the first region, locate at a side of the isolation structure adjacent to the substrate in the second region and connecting with the isolation structure; a well region formed in the substrate in the second region; a drift region formed in the substrate in the first region and enclosing the isolation structure and the compensation doping region; a gate structure formed over the substrate in a boundary region between the first region and the second region; a source region formed in the well region at one side of the gate structure; and a drain region formed in the drift region at another side of the gate structure.

Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a first region for forming a first transistor and a second region for forming a second transistor, the first transistor having a working current less than the second transistor. The fabrication method further includes forming a gate electrode layer on the base substrate; etching the gate electrode layer to form a first gate electrode in the first region; after forming the first gate electrode, etching the gate electrode layer to form a second gate electrode in the second region, with the second gate electrode having an undercut structure; forming a first source/drain doped region in the base substrate on both sides of the first gate electrode and forming a second source/drain region in the base substrate on both sides of the second gate electrode.

Abstract: A clamping system, a wire bonding machine and a method for bonding wires are provided. An exemplary clamping system includes a clamping device. The clamping device includes: at least one linear guide rail; a first clamping rod arranged perpendicular to the linear guide rail; and a second clamping rod arranged perpendicular to the linear guide rail and parallel to the first clamping rod.

Abstract: A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.

Abstract: A method for manufacturing the image sensor includes providing a substrate structure; forming a mask layer on the substrate structure, the mask layer having openings; depositing a metal grid material covering a surface of the mask layer and a bottom of the openings; and stripping the mask layer for removing a portion of the metal grid material on the top surface of the mask layer. The substrate structure includes: a substrate having a first surface; a plurality of pixels in the substrate; isolation structures around each of the plurality of pixels; and an anti-reflective coating on the first surface of the substrate. The openings include first openings exposing a portion of the first surface of the substrate structure above the isolation structures. A remaining portion of the metal grid material at the bottom of the openings forms metal grids.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.

Abstract: The present disclosure provides a semiconductor structure forming method, including: providing a base, a first mask layer and a second mask layer located at the top of the first mask layer being formed on the base, and the second mask layer internally having a first opening, a second opening and a third opening; forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening; forming a first pattern layer filling the first opening, the second opening and the third opening, the first pattern layer internally having a first groove; etching to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; and by using the second mask layer and the first side wall layers as masks, etching the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as

Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.

Abstract: A semiconductor device manufacturing method is presented. The manufacturing method includes providing a semiconductor structure, comprising: a substrate, a plurality of semiconductor fins comprising a first semiconductor fin and a second semiconductor fin on the substrate, a plurality of trenches surrounding the semiconductor fins, and a first insulation layer filling the trenches; conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein; removing at least a portion of the first insulation layer from the trenches; forming a second insulation layer filling a portion of the trenches not filled by the first insulation layer; and conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein. This inventive concept reduces the chance of a dopant in the first doping process diffusing into the second semiconductor fin.

Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.

Abstract: A semiconductor device and fabrication method are provided. The method includes providing a first dielectric layer with a first groove on a base substrate. A first gate electrode is formed in the first groove, with a top surface lower than the first dielectric layer. A first protective layer is formed on a portion of the top surface of the first gate electrode, with a first oxygen ionic concentration. A compensating protective layer is formed on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, with a second oxygen ionic concentration. A second dielectric layer is formed on the first protective layer, on the compensating protective layer, and on the first dielectric layer, with a third oxygen ionic concentration. The first oxygen ionic concentration and second oxygen ionic concentration are smaller than the third oxygen ionic concentration.