Abstract: A method for fabricating a semiconductor nanowire device includes forming a base including a plurality of PMOS regions, forming a plurality of first openings in the base of the PMOS regions, forming a plurality of first epitaxial wires by filling the first openings with a germanium-containing material, and forming a plurality of second openings in the base by etching a portion of the base under each first epitaxial wire. Each first epitaxial wire is connected to both sidewalls of a corresponding second opening and is hung above a bottom surface of the corresponding second opening. The method also includes performing a thermal oxidation treatment process on the plurality of first epitaxial wires to form an oxide layer on each first epitaxial wire, forming a plurality of first nanowires by removing the oxide layer from each first epitaxial wire, and forming a first wrap-gate structure to surround each first nanowire.

Abstract: A comparator and a successive approximation analog-to-digital converter are provided. The comparator includes a pre-operational amplifier, a latch, a level shift unit, and a reset unit. The pre-operational amplifier receives a to-be-compared signal, and outputs a first-stage amplification signal and a latch clock signal. The latch includes a first inverter circuit and a second inverter circuit, receives and compares the first-stage amplification signal, and outputs a comparison result signal. The level shift unit includes a first level shift circuit and a second level shift circuit, and generates a potential difference between working transistors in the first inverter circuit and the second inverter circuit, respectively. The reset unit includes a first reset circuit and a second reset circuit, and resets a voltage of a node where the level shift unit, the first inverter circuit and the second inverter circuit are coupled when the latch clock signal is at a low level.

Abstract: The present disclosure provides test structures, fabrication methods thereof and test methods thereof. An exemplary test structure includes a substrate having a to-be-tested region having at least one fin and a peripheral region having at least one fin surrounding the to-be-tested region; an insulation layer covering portions of side surfaces of the fins; at least one first gate structure covering side and top surfaces of the fin in the to-be-tested region; second gate structures covering side and top surfaces of the fins in the peripheral region; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the first gate structure and adjacent second gate structures; and a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region. The plurality of first conductive structures cross over and are on source/drain regions of at least two fins.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a first dielectric layer having a first thickness on the semiconductor substrate, forming a first opening having a first width in the first dielectric layer and exposing a surface of the semiconductor substrate, forming a spacer on opposite sidewalls of the first opening, forming a second dielectric layer having a second thickness on the exposed surface of the semiconductor substrate in a middle region of the first opening, removing the spacer to form a second opening having a first opening portion and a second opening portion on opposite sides of the second dielectric layer, and forming a third dielectric layer having a third thickness on the first and second opening portions of the second opening. The third thickness is smaller than the first thickness and the second thickness.

Abstract: A method for repairing a lithography mask includes determining a defect region in the mask, selecting a predetermined peripheral region of the defect region, depositing a barrier layer on the predetermined peripheral region, and repairing the defect region. The mask may be a MoSi-binary type mask. The barrier layer may compensate for uncertainty occurring during the repair of the defect region. Because the repair processes only require determining the defect region and forming the barrier layer on the periphery of the defect region, and etching the defect, the novel method has a shorter repair time period, better repair effect and improved repair efficiency than conventional methods.

Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.

Abstract: Memory cells and fabrication methods thereof are provided. An exemplary method includes providing a substrate having a well region; forming a select gate structure, a floating gate structure and a dummy gate structure on a surface of the well region; forming a first lightly doped region, a second lightly doped region and a third lightly doped region in the well region, the first lightly doped region and the second lightly doped region being at two sides of the select gate structure respectively, the second lightly doped region being in between the select gate structure and the floating gate structure, and the third lightly doped region being in between the floating gate structure and the dummy gate structure; and forming bit line region in the first lightly doped region and a source region in the third lightly doped region, the source region being enclosed by the third lightly doped region.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate, where an opening is formed in the dielectric layer, and bottom of the opening exposes surface of the substrate. The method also includes forming a first metal layer over of the dielectric layer, where a temperature for forming the first metal layer is a first temperature. In addition, the method includes forming a second metal layer filling the opening, where a temperature for forming the second metal layer is a second temperature, and the second temperature is higher than the first temperature. Further, the method includes planarizing the second metal layer and the first metal layer until the top surface of the dielectric layer is exposed.

Abstract: A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first dielectric layer positioned between the substrate and the first metal member, a first barrier layer positioned between the first dielectric layer and the first metal member, a first first-type work function layer directly contacting the first barrier layer and positioned between the first barrier layer and the first metal member, and a first second-type work function layer directly contacting both the first first-type work function layer and the first metal member. The n-channel device may include a second metal member, a second dielectric layer positioned between the substrate and the second metal member, and a second second-type work function layer directly contacting both the second dielectric layer and the second metal member.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.

Abstract: An alignment method and an alignment system are provided. The alignment method includes: providing a wafer including an exposed surface, wherein an alignment mark and a reference point with a reference distance are provided on the exposed surface; placing the wafer on a reference plane; performing an alignment measurement on the exposed surface to obtain a projection distance, configured as a measurement distance, between the alignment mark and the reference point on the reference plane; performing a levelling measurement between the exposed surface and the reference plane to obtain levelling data of the exposed surface; obtaining a distance, configured as an expansion reference value, between the alignment mark and the reference point in the exposed surface; obtaining an expansion compensation value based on a difference between the expansion reference value and the reference distance; and adjusting parameters of a photolithography process based on the expansion compensation value for an alignment.

Abstract: A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on the first region and a third portion of the second type on the second region. A first gate structure surrounds the second portion and the third portion. A first work function adjusting layer is on the gate insulator layer on the first and second portions. A second work function adjusting layer is on the first work function adjusting layer, the gate insulator layer on the third portion, and the first insulator layer. The device also includes a gate on the second work function adjusting layer, a hardmask layer on the gate, and an interlayer dielectric layer surrounding the gate structure.

Abstract: A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.

Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.

Abstract: A method for fabricating a metal gate transistor includes forming a dummy gate structure surrounded by a first dielectric layer on a semiconductor substrate and a source/drain region in the semiconductor substrate on each side of the dummy gate structure. The top surface of the dummy gate structure is leveled with the top surface of the first dielectric layer. The method then includes forming an etch stop sidewall in the first dielectric layer on each side of the dummy gate structure, forming a first trench by removing the dummy gate structure, and forming a metal gate structure to partially fill the first trench. The top portion of the first trench becomes a second trench. Further, the method also includes forming an etch stop layer by filling the second trench, and then forming a contact plug in the first dielectric layer to electrically connect to each source/drain region.

Abstract: A method for fabricating a Fin-FET device includes forming fin structures with each having a gate structure on the top in both P-type regions and N-type regions, forming a first epitaxial layer on each fin structure on both sides of the gate structure in the P-type regions, forming a P-type doped first covering layer on each first epitaxial layer, forming a second epitaxial layer on each fin structure on both sides of the gate structure in the N-type regions, forming an N-type doped second covering layer on each second epitaxial layer, and forming a titanium-containing silicification layer on the first covering layer and the second covering layer. The method further includes performing a first annealing process to let titanium ions in the silicification layer diffuse into the first covering layer to form a first metal silicide layer and into the second covering layer to form a second metal silicide layer.

Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.

Abstract: The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate. Forms of the present disclosure can reduce loss of impurities implanted by the threshold voltage adjustment ion implantation.

Abstract: A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a divided voltage and a clock oscillator providing a drive clock signal for the charge pump circuit. In addition, the charge pump voltage regulator includes a first voltage comparator circuit suitable to output at least one of a first comparison result and a second comparison result. Further, the charge pump voltage regulator includes a logic control unit, where, when the charge pump voltage regulator operates in a standby mode, the logic control unit outputs a first control level to the clock oscillator according to the at least one of the first comparison result and the second comparison result.