Abstract: A semiconductor device and a manufacturing method therefor are provided. The semiconductor device includes a semiconductor substrate including a trench used for a source/drain region; and a SiGe seed layer formed simultaneously on the sidewall and bottom of the trench, and the SiGe seed layer on the sidewall of the trench has an uneven thickness with a maximum thickness at a location corresponding to the channel region in the semiconductor substrate. The semiconductor device and the manufacturing method therefor according to the present disclosure enable the SiGe seed layer to block diffusion of elements such as boron more effectively.

Abstract: An interface device may include a first transistor, a pull-up unit, a pull-down unit, a first power supply terminal, a ground terminal, an output signal terminal, and a bias unit. A first gate terminal of the pull-up unit is electrically connected to a source terminal of the first transistor. A drain terminal of the pull-down unit is electrically connected to a drain terminal of the first transistor. The first power supply terminal is electrically connected to a source terminal of the pull-up unit. The ground terminal is electrically connected to a source terminal of the pull-down unit. The output signal terminal is electrically connected to each of a drain terminal of the pull-up unit and the drain terminal of the pull-down unit. An output terminal of the bias unit is electrically connected, without any intervening transistor, to a gate terminal of the first transistor.

Abstract: An integrated circuit includes a semiconductor substrate, and at least two transistors connected in series on the semiconductor substrate, wherein each transistor shares a source electrode or a drain electrode with an adjacent transistor. The integrated circuit also includes a hermetic cavity disposed on the source electrode and the drain electrode, between gate electrodes of adjacent transistors. The source electrode disposed at a first end portion of the series of transistors is in direct contact with a source interconnect, and the drain electrode disposed at a second end portion of the series of transistors is in direct contact with a drain interconnect.

Abstract: An exposure apparatus is provided for performing a column scan-exposure process. The exposure apparatus includes a base for supporting the exposure apparatus; and a reticle stage configured for holding a reticle having at two mask pattern regions and carrying the reticle to move reciprocally along a scanning direction. The exposure apparatus also includes a wafer stage configured for holding a wafer and carrying the wafer to move reciprocally along the scanning direction. Further, the exposure apparatus includes a control unit configured to control the reticle stage and the wafer stage to cooperatively move to cause the at least two mask pattern regions of the reticle on the reticle stage to be continuously and sequentially projected on at least two corresponding exposure shots of the wafer on the wafer stage along the scanning direction to perform a column scan-exposure process.

Abstract: Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate. The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate.

Abstract: An elastic retention wheel and a wafer adapter containing this wheel are disclosed. The elastic retention wheel comprises: a rim; a retention main body positioned within the rim; and a plurality of spokes. Each spoke is positioned in a space between the rim and the retention main body. One end of each spoke is coupled to the retention main body, and the other end is coupled to the rim. A sliding rail can be provided on an inner side of the rim, and the spoke's other end can slide with the sliding rail. When the elastic retention wheel is stressed by a non-uniform or excessive external force, these spokes provide enhanced support from the rim's inner side, or at least partially disperse the non-uniform external force applied to the elastic retention wheel. Thereby, the elastic retention wheel is largely kept from over-deformation or cracking.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube portion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.

Abstract: A standard wafer is provided including a substrate; a first layer of semiconductor material formed on the substrate; a bar formed over the first layer of semiconductor material with an interlayer interposed therebetween; and a first sidewall spacer and a second sidewall spacer formed on the opposite sides of the bar respectively, in which the bar and the first layer of semiconductor material are formed of a same semiconductor material, and the interlayer interposed between the first layer of semiconductor material and the bar is formed of a first oxide, and the first sidewall spacer and the second sidewall spacer are formed of a second oxide. A corresponding fabrication method of the standard wafer is also provided.

Abstract: A laser annealing device for compensating wafer heat maps and its method are disclosed. A laser annealing device comprises a pump laser source array including of a plurality of pump laser sources for irradiating a tunable mask, each pump laser source emitting pump laser, an annealing laser source for emitting annealing laser and irradiating the tunable mask, and a tunable mask for transmitting at least part of the annealing laser after being irradiated by the pump laser.

Abstract: A method and an apparatus for monitoring an electron beam condition of an SEM are provided. The SEM includes an electron gun and an electromagnetic lens system. The method includes acquiring quality parameters of an input electron beam, wherein the input electron beam is provided by the electron gun to the electromagnetic lens system, acquiring a current set of operation parameters of the electromagnetic lens system, calculating quality parameters of an output electron beam of the electromagnetic lens system, based on the quality parameters of the input electron beam and one or more operation parameters of the current set of operation parameters, and determining, based on the quality parameters of the output electron beam, whether calibration of the SEM is required.

Abstract: A semiconductor device includes a substrate, a first barrier layer disposed on the substrate, a first dielectric layer disposed on the first barrier layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device further includes a third barrier layer and a first metal gate each being disposed between a first portion of the second barrier layer and a second portion of the second barrier layer. The first metal gate is disposed between the third barrier layer and the substrate. The semiconductor device further includes a second dielectric layer. The third barrier layer is disposed between the first metal gate and the second dielectric layer. The semiconductor device further includes a second metal gate. The semiconductor device further includes a contact hole positioned between the first metal gate and the second metal gate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.

Abstract: A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance.

Abstract: A device that may be used for a phase change random access memory in a semiconductor device and a manufacturing method thereof are provided. The device includes a phase change unit and two sidewall electrodes respectively located on two opposite sidewalls of the phase change unit. The phase change unit includes a three layer structure, in which a phase change material layer is positioned between a top insulating material layer and a bottom insulating material layer. The first sidewall electrode and the second sidewall electrode are in contact with two opposite end faces of the phase change material layer. The contact area between electrode and phase change material is reduced, thereby obtaining a relatively small drive current and meeting a demand that the integrated level of such a device is increasingly enhanced.

Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.

Abstract: A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via.