Abstract: This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode.

Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.

Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.

Abstract: A method of fabricating a miniaturized semiconductor or other such device takes advantage of a self-reorganization characteristic of an in-situ dissociable diblock copolymer to form a circular via hole that is centrally disposed relative to other device features. In one embodiment, the method is used to form a dual damascene structure. During formation of the dual damascene structure, due to the self-reorganization characteristics of the monomer constituents of the diblock copolymer, the position of the via hole can be ensured to be self aligned with the position of the trench, thus improving the performance and yield of the so formed semiconductor devices, and lowering fabrication costs.

Abstract: The present invention discloses a phase change memory and a manufacturing method thereof. The phase change memory according to the present invention uses top electrodes provided on the top of storage nodes to heat the storage nodes such that a phase change layer in the storage nodes undergoes a phase change. In the phase change memory of embodiments of the present invention, the contact area between the top electrode and the storage node is relatively small, which is good for phase change. Moreover, each column of storage nodes is connected by the same linear top electrode, which can improve photo alignment shift margin.

Abstract: An elastic retention wheel and a wafer adapter containing this wheel are disclosed. The elastic retention wheel comprises: a rim; a retention main body positioned within the rim; and a plurality of spokes. Each spoke is positioned in a space between the rim and the retention main body. One end of each spoke is coupled to the retention main body, and the other end is coupled to the rim. A sliding rail can be provided on an inner side of the rim, and the spoke's other end can slide with the sliding rail. When the elastic retention wheel is stressed by a non-uniform or excessive external force, these spokes provide enhanced support from the rim's inner side, or at least partially disperse the non-uniform external force applied to the elastic retention wheel. Thereby, the elastic retention wheel is largely kept from over-deformation or cracking.

Abstract: A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element.

Abstract: Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure.

Abstract: Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

Abstract: A test structure in accordance with the present invention allows for testing of both Vbd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of parallel polysilicon gate structures overlying a substrate. Traces placing alternate gates in electrical communication with a polysilicon edge are connected by a fuse. In one embodiment, a potential difference is applied across all gates to trigger Vbd, and then the fuse is broken to allow individual probing of breakdown of the alternate groups of gates. In another embodiment, the fuse is broken and then force and sense voltages are applied to the edge polysilicon in communication with the alternate gate groupings, allowing detection of leakage current between the alternate groupings of gates that reveals the existence of an unwanted polysilicon extrusion or bridge.

Abstract: The present invention discloses a high voltage tolerant output buffer, which is compatible with a 5-volt input signal on its output node while operating with a 3.3-volt power supply. The high voltage tolerant output buffer includes a NAND gate, a NOR gate, a pair of pull-up transistors, a pair of pull-down transistors, a pair of enable transistors, an inhibit transistor, and a substrate bias circuit. The present invention overcomes the problems due to the degradation of gate-oxide integrity reliability and reduces the fabrication cost by minimizing the chip size.