Abstract: This disclosure relates to a metal-insulator-metal capacitor structure and a method for forming the same. The metal-insulator-metal capacitor structure includes: a first capacitor dielectric layer, located on a first electrode layer; a second electrode layer, located on the first capacitor dielectric layer in a first capacitor region; and one or more capacitor stacks, located on the second electrode layer in the first capacitor region. Each of the capacitor stacks includes a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer. Projection overlay regions exist between the third electrode layer and the second electrode layer and between the adjacent third electrode layers. The one or more second capacitor dielectric layers are further located on the first capacitor dielectric layer in the second capacitor region disclosure.

Abstract: A capacitor structure and a forming method thereof are provided. The capacitor structure includes a substrate and a bottom electrode composite layer on the substrate. The bottom electrode composite layer includes a first electrode layer and a second electrode layer on the first electrode layer. An oxidation rate of a material of the second electrode layer is lower than an oxidation rate of a material of the first electrode layer. The capacitor structure also includes a dielectric structure layer on the bottom electrode composite layer.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate structure including a device region, a first interconnection structure, and a plurality of third interconnection layers. The device region includes a plurality of first regions and one or more second regions that are arranged along a first direction. The first interconnection structure includes a plurality of first interconnection layers and a plurality of second interconnection layers that are extended along a second direction. A first interconnection layer has a length greater than a second interconnection layer in the second direction, and the first direction is perpendicular to the second direction. A third interconnection layer is disposed over the second region, and the third interconnection layer is electrically interconnected with the second interconnection layer.

Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; gate structures and source/drain plugs over the base substrate; source/drain contact structures on the source/drain plugs; gate contact structures on the gate structures; and a dielectric layer on the gate structures and the source/drain plugs. Cavities are formed between the gate structures and the source/drain plugs along a surface of the base substrate. The dielectric layer encloses tops of the cavities.

Abstract: A wet etching method is provided in the present disclosure. The method includes providing a substrate, where a layer to-be-etched is on a surface of the substrate; and performing etching treatments on the layer to-be-etched till a thickness of the layer to-be-etched reaches a target thickness. Each etching treatment includes performing a first etching process, where the substrate is at a first rotation speed; after the first etching process, performing a second etching process, where a rotation speed of the substrate is reduced from the first rotation speed to a second rotation speed, and a liquid film of a chemical solution on the surface of the substrate is increased to a first thickness; and after the second etching process, performing a third etching process, where the substrate is at a third rotation speed, and the third rotation speed is lower than or equal to the first rotation speed.

Abstract: A semiconductor structure and a method for forming the same are provided. One form of a semiconductor structure includes: a substrate including a device unit region, where the device unit region includes a first sub-unit region configured to form a first device and a second sub-unit region configured to form a second device, where a driving current of the first device is greater than a driving current of the second device; a fin protruding from the substrate; a first gate spanning the fin in the first sub-unit region; and a second gate spanning the fin in the second sub-unit region. In some implementations, the second sub-unit region is disposed in the device unit region, and the second device generates less heat than the first device. Therefore, compared with a solution in which the device unit region includes only a first device region, overall heat from the device unit region can be reduced, thus ameliorating a self-heating effect in the device unit region and enhancing the performance of semiconductors.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, a gate structure over the substrate, and a sidewall spacer structure located on a sidewall surface of the gate structure. The sidewall spacer structure includes a first sidewall spacer, a second sidewall spacer, and a cavity located between the first sidewall spacer and the second sidewall spacer. The first sidewall spacer is located on the sidewall surface of the gate structure. A top surface of the cavity is above a top surface of the gate structure, and a bottom surface of the cavity is coplanar with a bottom surface of the gate structure. The semiconductor structure also includes a source and drain plug located over the substrate on each side of the gate structure. The source and drain plug is located on a sidewall surface of the second sidewall spacer.

Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.

Abstract: A semiconductor device and a forming method thereof are provided. The forming method includes forming an initial dummy gate structure on a substrate. The initial dummy gate structure extends along a first direction. The forming method also includes forming a source/drain doped layer in the substrate on two sides of the initial dummy gate structure, forming an initial conductive layer on the source/drain doped layer and covering a sidewall and a top surface of the source/drain doped layer, and after forming the initial conductive layer, removing the initial dummy gate structure.

Abstract: A semiconductor structure includes: a channel protrusion structure, suspended on a base, including channel layers arranged at intervals along a longitudinal direction; a gate structure, spanning the channel protrusion structure and covering part of a top and part of a side wall of the channel protrusion structure, surrounding and covering the channel layers, the gate structure located between adjacent channel layers in the longitudinal direction and between adjacent channel layers and the base serving as an inner gate structure, and the inner gate structure and the adjacent channel layers, and/or, the inner gate structure, the adjacent channel layers and the base forming an inner trench; an inner spacer, located in the inner trench; and a source/drain doped layer, located on the base and connected to two ends of the channel layer, the source/drain doped layer and the inner spacer having a gap therebetween used as an air spacer.

Abstract: A semiconductor structure includes: a base, a first and a second electrode layer, where the first electrode layer is located on the base and includes a first comb handle part and a plurality of first comb tooth parts connected to the first comb handle part and arranged in parallel, one end of the first comb handle part is configured to access an input signal, and the other end is configured to access an output signal; and the second electrode layer is located on the base and located on the same layer with the first electrode layer, and includes a second comb handle part and a plurality of second comb tooth parts connected to the second comb handle part and arranged in parallel, the second comb tooth parts and the first comb tooth parts are parallel in a crossed manner, and the second comb handle part is configured to be grounded.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a base substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction layer on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction layer. An opening is formed at least exposing a portion of one of an upper surface and a lower surface of the magnetic tunnel junction layer.

Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes: a substrate and a magnetic tunnel junction on the substrate. The magnetic tunnel junction includes: a bottom electromagnetic structure on the substrate, an insulating layer on the bottom electromagnetic structure, and a top electromagnetic structure on the insulating layer. The semiconductor structure further includes a sidewall tunneling layer on sidewall surfaces of the magnetic tunnel junction.

Abstract: Semiconductor structures and fabrication methods are provided. The method includes providing a to-be-etched layer having first regions, second regions and third regions; forming a first core layer on a first region; forming a first sidewall spacer on sidewalls of the first core layer; forming a sacrificial layer covering a portion of the first sidewall spacer on the to-be-etched layer, having a plurality of initial first openings and with a portion of the initial first opening exposing a portion of the first sidewall spacer on the second region; removing the portion of the first sidewall spacer exposed by the portion of the initial first opening to form a first opening; forming a second sidewall spacer in the first opening; and forming second openings in the sacrificial layer. The second openings expose one of or both a portion of the first sidewall spacer and a portion of the second sidewall spacer.

Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fu

Abstract: A semiconductor structure and a fabrication method thereof. The semiconductor structure, includes: a substrate; and magnetic tunnel junctions on the substrate, that each magnetic tunnel junction of the magnetic tunnel junctions includes a first region and a second region adjacent to the first region, each magnetic tunnel junction includes a multilayered material including material layers stacked along a normal direction of the substrate, and the material layers of each magnetic tunnel junction include at least one material layer that is different in the first region and the second region. The storage capacity density of the semiconductor structure is high.

Abstract: Semiconductor structure is provided. The semiconductor structure includes a substrate including device regions and an isolation region located adjacent to and between the device regions; a fin on the substrate; gate structures across the fin at the device regions; source/drain doped regions in the fin at two sides of each of the gate structures; a first opening in the fin at the isolation region; and an insulation structure located in the first opening. Two opposite sidewalls of the first opening are respectively in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.

Abstract: A method for forming a semiconductor structure in provided. The method includes providing a substrate, forming a gate electrode layer on the substrate, and performing a defluorination treatment on the gate electrode layer. The method also includes, after performing the defluorination treatment, forming a barrier layer on a portion of a surface of the gate electrode layer. The barrier layer is made of a material including titanium element.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.