Patents Assigned to Semiconductor Manufacturing International (Shanghai) Corporation
  • Publication number: 20240332400
    Abstract: A semiconductor structure includes: a channel protrusion structure, suspended on a base, including channel layers arranged at intervals along a longitudinal direction; a gate structure, spanning the channel protrusion structure and covering part of a top and part of a side wall of the channel protrusion structure, surrounding and covering the channel layers, the gate structure located between adjacent channel layers in the longitudinal direction and between adjacent channel layers and the base serving as an inner gate structure, and the inner gate structure and the adjacent channel layers, and/or, the inner gate structure, the adjacent channel layers and the base forming an inner trench; an inner spacer, located in the inner trench; and a source/drain doped layer, located on the base and connected to two ends of the channel layer, the source/drain doped layer and the inner spacer having a gap therebetween used as an air spacer.
    Type: Application
    Filed: March 25, 2024
    Publication date: October 3, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Bo SU, Hansu OH
  • Publication number: 20240313042
    Abstract: A semiconductor structure includes: a base, a first and a second electrode layer, where the first electrode layer is located on the base and includes a first comb handle part and a plurality of first comb tooth parts connected to the first comb handle part and arranged in parallel, one end of the first comb handle part is configured to access an input signal, and the other end is configured to access an output signal; and the second electrode layer is located on the base and located on the same layer with the first electrode layer, and includes a second comb handle part and a plurality of second comb tooth parts connected to the second comb handle part and arranged in parallel, the second comb tooth parts and the first comb tooth parts are parallel in a crossed manner, and the second comb handle part is configured to be grounded.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 19, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yichao WU, Jisong JIN
  • Patent number: 12096696
    Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a base substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction layer on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction layer. An opening is formed at least exposing a portion of one of an upper surface and a lower surface of the magnetic tunnel junction layer.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: September 17, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Patent number: 12087582
    Abstract: Semiconductor structures and fabrication methods are provided. The method includes providing a to-be-etched layer having first regions, second regions and third regions; forming a first core layer on a first region; forming a first sidewall spacer on sidewalls of the first core layer; forming a sacrificial layer covering a portion of the first sidewall spacer on the to-be-etched layer, having a plurality of initial first openings and with a portion of the initial first opening exposing a portion of the first sidewall spacer on the second region; removing the portion of the first sidewall spacer exposed by the portion of the initial first opening to form a first opening; forming a second sidewall spacer in the first opening; and forming second openings in the sacrificial layer. The second openings expose one of or both a portion of the first sidewall spacer and a portion of the second sidewall spacer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 10, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Patent number: 12089501
    Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes: a substrate and a magnetic tunnel junction on the substrate. The magnetic tunnel junction includes: a bottom electromagnetic structure on the substrate, an insulating layer on the bottom electromagnetic structure, and a top electromagnetic structure on the insulating layer. The semiconductor structure further includes a sidewall tunneling layer on sidewall surfaces of the magnetic tunnel junction.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 10, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ming Zhou
  • Patent number: 12080596
    Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fu
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 3, 2024
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jisong Jin, Abraham Yoo
  • Patent number: 12075705
    Abstract: A semiconductor structure and a fabrication method thereof. The semiconductor structure, includes: a substrate; and magnetic tunnel junctions on the substrate, that each magnetic tunnel junction of the magnetic tunnel junctions includes a first region and a second region adjacent to the first region, each magnetic tunnel junction includes a multilayered material including material layers stacked along a normal direction of the substrate, and the material layers of each magnetic tunnel junction include at least one material layer that is different in the first region and the second region. The storage capacity density of the semiconductor structure is high.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: August 27, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Wen Bin Xia
  • Patent number: 12074163
    Abstract: Semiconductor structure is provided. The semiconductor structure includes a substrate including device regions and an isolation region located adjacent to and between the device regions; a fin on the substrate; gate structures across the fin at the device regions; source/drain doped regions in the fin at two sides of each of the gate structures; a first opening in the fin at the isolation region; and an insulation structure located in the first opening. Two opposite sidewalls of the first opening are respectively in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: August 27, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wu Feng Deng, De Biao He, Chang Yong Xiao
  • Patent number: 12068163
    Abstract: A method for forming a semiconductor structure in provided. The method includes providing a substrate, forming a gate electrode layer on the substrate, and performing a defluorination treatment on the gate electrode layer. The method also includes, after performing the defluorination treatment, forming a barrier layer on a portion of a surface of the gate electrode layer. The barrier layer is made of a material including titanium element.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: August 20, 2024
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Hua Wang, Changyong Xiao, Yihui Lin, Qin Zhang, Yi Lu, Xiang Hu, Xiaona Zhu, Ying Jiang
  • Patent number: 12068397
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: August 20, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Xiang Hu
  • Publication number: 20240274175
    Abstract: Provided are a magnetic random access memory cell and a magnetic random access memory. One form of a memory cell includes: a spin-orbit torque (SOT) layer, through which a write current flows when performing a write operation on the magnetic random access memory cell, a direction of the write current being a first direction, and a direction parallel to the SOT layer and perpendicular to the first direction being a second direction; and a magnetic tunnel junction, located on the SOT layer, the magnetic tunnel junction including substructures symmetrical with respect to the second direction, and a magnetic moment direction of the substructure forming an acute included angle with the first direction.
    Type: Application
    Filed: July 7, 2023
    Publication date: August 15, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240274466
    Abstract: In one form, a method includes: providing a base, where a bottom film layer structure is formed on the base and includes a plurality of discrete first regions and a plurality of second regions located among the first regions; forming top conductive layers on the bottom film layer structure of the first regions, where openings are enclosed between the adjacent top conductive layers and the bottom film layer structure; forming grooves in the bottom film layer structure at bottoms of the openings, where bottoms of the grooves are lower than bottoms of the top conductive layers; and forming a first dielectric layer on the top conductive layers, where the first dielectric layer is further located in the grooves, seals tops of the openings and encloses air gaps together with the openings, and bottoms of the air gaps are lower than the bottoms of the top conductive layers.
    Type: Application
    Filed: May 31, 2023
    Publication date: August 15, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yichao WU, Jisong JIN
  • Publication number: 20240276889
    Abstract: Provided are a magnetic random access memory cell and a magnetic random access memory. In one form, a memory cell includes: a spin-orbit torque (SOT) layer, through which a write current flows when performing a write operation on the magnetic random access memory cell; a magnetic tunnel junction, located on the SOT layer; a first bottom plug, located on a bottom of the SOT layer and contacting one end of the SOT layer, and a second bottom plug, located on the bottom of the SOT layer and spaced apart from the first bottom plug, the second bottom plug contacting the other end of the SOT layer, and an arrangement direction of the second bottom plug and the first bottom plug forming an acute included angle with a magnetic moment direction of the magnetic tunnel junction.
    Type: Application
    Filed: July 7, 2023
    Publication date: August 15, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Patent number: 12051737
    Abstract: Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalls of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 30, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 12048133
    Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: July 23, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 12022740
    Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate, where the substrate includes a conductive layer therein, and a surface of the substrate exposes a surface of the conductive layer; forming a groove adjacent to the conductive layer in the substrate, where the groove exposes a portion of a sidewall surface of the conductive layer; and forming a lower electrode layer in the groove and on a top surface of the conductive layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: June 25, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ming Zhou
  • Patent number: 12015067
    Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; a gate structure on the base substrate, including a first portion in a first region and a second portion in a second region; and one or more stop layers on the base substrate and located in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: June 18, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Publication number: 20240186233
    Abstract: A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; forming a first redistribution structure on the carrier, the first redistribution structure including a first area and a second area; forming a conductive pillar on the first redistribution structure in the first area, the conductive pillar being electrically connected to the first redistribution structure; providing a device chip, including a first side and a second side opposite to the first side; bonding the second side of the device chip to the first redistribution structure in the second area, the device chip being electrically connected to the first redistribution structure; providing a substrate including a bonding surface; and bonding the first side of the device chip and the conductive pillar to the bonding surface, the device chip being electrically connected to the substrate, and the conductive pillar being electrically connected to the substrate.
    Type: Application
    Filed: November 21, 2023
    Publication date: June 6, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240186253
    Abstract: A packaging structure and a packaging method are provided The packaging method includes: bonding a first interconnect chip to a carrier plate in a first area; bonding a first side of a device chip to the carrier plate in a second area, a first chip area of the device chip being adjacent to the first interconnect chip; bonding a second interconnect chip to the first interconnect chip and the first chip area, the second interconnect chip being electrically connected to the first interconnect chip and the device chip, and the second interconnect chip exposing a second chip area; removing the carrier plate; and bonding the first side of the device chip and a side of the first interconnect chip to a bonding surface of a substrate, the first side of the device chip and the first interconnect chip being electrically connected to the substrate.
    Type: Application
    Filed: November 21, 2023
    Publication date: June 6, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240178186
    Abstract: A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; providing a plurality of device chips, a device chip including a first side and a second side, and a first interconnection structure being formed on the first side; attaching the plurality of device chips to the carrier; forming a first packaging layer covering a side wall of the device chip and filling between device chips on the carrier; providing an interconnect chip, a second interconnection structure being formed on the interconnect chip, and the second interconnection structure exposing a surface of the interconnect chip; bonding the interconnect chip to the device chip and the first packaging layer, the second interconnection structure of the interconnect chip facing and contacting the first interconnection structure of the device chip; and forming a second packaging layer covering the interconnect chip on the first packaging layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: May 30, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN