Patents Assigned to Semiconductor Manufacturing International (Shanghai) Corporation
  • Publication number: 20200203479
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor apparatus and manufacturing methods for the same.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hai Zhao
  • Patent number: 10692779
    Abstract: A method for forming a semiconductor device includes providing a substrate, the substrate including a first trench in an NMOS region and a second trench in a PMOS region. The method also includes depositing a high-K dielectric layer, a cap layer, and a P-type work function metal layer on the bottom and side walls of the first trench and the second trench, removing the P-type work function metal layer and the cap layer from the bottom and sidewalls of the first trench, depositing an N-type work function metal layer on the high-K dielectric layer in the first trench and on the P-type work function metal layer in the second trench, and depositing a metal electrode layer on the N-type work function metal layer.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 23, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10693431
    Abstract: A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a lower electrode layer and a second dielectric layer; forming a piezoelectric film and an upper electrode layer in an opening in the second dielectric layer; forming a third dielectric layer; forming a first cavity in the third dielectric layer to expose at least part of the upper electrode layer; bonding a first assistant substrate to seal the first cavity; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer on a side of the isolation trench; and etching through the fourth dielectric layer, the isolation trench layer, the first dielectric layer to form a second cavity beneath the lower electrode layer, plan views of the first and second cavities providing an overlapped region having a polygon shape without parallel sides.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: June 23, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Herb He Huang, Clifford Ian Drowley, Jiguang Zhu, Haiting Li
  • Patent number: 10692731
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region and a second region; forming a first filling layer on the first region of the base substrate and a first hard mask layer on the first filling layer; performing a first treatment process on the second region of the base substrate using the first hard mask layer and the first filling layer as a mask; forming a second filling layer on the first region of the base substrate and a second mask on at least the second filling layer; removing the first hard mask layer and the first filling layer to expose the first region of the base substrate and to pattern the second hard mask layer on the second filling layer; and performing a second treatment process on the first region of the base substrate.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: June 23, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Cheng Long Zhang, Shi Liang Ji
  • Patent number: 10692992
    Abstract: Semiconductor device and fabrication method are provided. The fabrication method includes: providing a base substrate having a first gate dielectric film thereon; forming a first gate electrode layer on a portion of the first gate dielectric film; forming an offset sidewall film on the first gate dielectric film and covering sidewalls of the first gate electrode layer; forming lightly doped regions in the base substrate on sides of the first gate electrode layer; removing the offset sidewall film and a portion of the first gate dielectric film to form a first dielectric layer under the first gate electrode layer; forming sidewall spacers; forming source/drain doped regions on sides of the first gate electrode layer; forming a dielectric layer over the source/drain doped regions and the base substrate; and forming a gate opening in the dielectric layer by removing the first gate electrode layer and the first gate dielectric layer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 23, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Huan Yun Zhang, Jian Wu
  • Patent number: 10689246
    Abstract: A semiconductor device includes a bottom substrate, a sacrificial layer on the bottom substrate and including a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate, a top substrate on the sacrificial layer and on the second opening forming a cavity, a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer defining one or more pads. The pad includes a stack-layered structure of a first metal layer on the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer. The thus formed structure reduces the pad contact resistance.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 23, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chao Zheng, Wei Wang
  • Patent number: 10686422
    Abstract: A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a first metal connecting layer, a piezoelectric film, and an upper electrode layer; forming an acoustic resonance film by patternizing the piezoelectric film, the upper electrode layer, and the first metal connecting layer; above the base substrate, forming a second dielectric layer and a third dielectric layer; forming a first cavity through the third and second dielectric layers, and the protection layer; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer under the isolation trench layer; and forming a second cavity through the fourth dielectric layer, the isolation trench layer, and the first dielectric layer, plan views of the first and second cavities forming an overlapped region having a polygon shape without parallel sides.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Herb He Huang, Clifford Ian Drowley, Jiguang Zhu, Haiting Li
  • Patent number: 10685831
    Abstract: A semiconductor structure includes providing a substrate including a first surface and a second surface opposite to the first surface. The first surface is a functional surface. The method also includes forming a plastic seal layer on the first surface of the substrate, and performing a thinning-down process on the second surface of the substrate after forming the plastic seal layer. The plastic seal layer provides support for the substrate during the thinning-down process, and thus warping or cracking of the plastic seal layer 240 may be avoided. In addition, the plastic seal layer can also be used as a material for packaging the substrate. Therefore, after the thinning-down process, the plastic seal layer does not need to be removed. As such, the fabrication process is simplified, and the production cost is reduced.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Fu Cheng Chen, Jian Gang Lu
  • Patent number: 10686055
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a well region and a drift region in the semiconductor substrate; and forming one or more counter-doped regions in the drift region, the one or more counter-doped regions being aligned along a direction vertical to the semiconductor substrate to divide the drift region into a plurality of parts. The semiconductor fabrication method also includes: forming a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and forming a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Lei Fang
  • Patent number: 10685965
    Abstract: A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10685889
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10686081
    Abstract: This application relates to the technical field of semiconductors, and discloses a semiconductor device, an MOS capacitor, and manufacturing methods therefor.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 10685962
    Abstract: Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacrturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xi Lin, Yi Hua Shen
  • Patent number: 10686078
    Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a substrate; forming first fins on the substrate; forming barrier layers covering sidewalls of the first fins; forming a first groove in each first between the adjacent first barrier layers; and forming a first inner epitaxial layer in each first groove. The first fin and the adjacent first barrier layers surround the corresponding first groove.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10679902
    Abstract: Semiconductor device and fabrication method are provided.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventors: Zhi Dong Wang, Cheng Long Zhang, Wu Tao Tu
  • Patent number: 10680079
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure on a base substrate and forming a first dielectric layer on the base substrate. The first dielectric layer has a top lower than the gate structure and exposes a sidewall portion of the gate structure. The method also includes forming an isolation sidewall spacer on the exposed sidewall portion of the gate structure.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10679881
    Abstract: An apparatus for detecting a mark having first and second stripe groups on a substrate includes a detection module moveable over a surface of the substrate. The detection module includes a detection unit and a positioning unit configured to align the detection unit with the mark. The detection unit is configured to obtain data of the mark and operative to perform repeated acquisition operations on the first and second stripe groups of the mark. Each of the acquisition operations acquires data associated with the first stripe group or the second stripe group. The apparatus also includes a processing module configured to determine a positional deviation between the first stripe group and the second stripe group in response to the obtained data of the mark and data associated with a motion of the detection module.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 9, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Qiang Wu, Xuan Liu, Shifeng He, Jianyao Liu
  • Patent number: 10679905
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first gate structures on a first region of a substrate, a plurality of second gate structures on a second region of the substrate, and a first stress layer on both sides of each first gate structure; forming a first-region mask layer on the first stress layer; forming a second stress layer on both sides of each second gate structure; forming a contact-hole etch stop layer on the second stress layer; forming a plurality of first contact holes on the first stress layer and a plurality of second contact holes on the second stress layer to expose the contact-hole etch stop layer; at least partially removing the contact-hole etch stop layer in each first contact hole; and removing the first-region mask layer in each first contact hole and the contact-hole etch stop layer in each second contact hole.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10672669
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, a plurality of trenches extending through the interlayer dielectric layer to the semiconductor substrate and comprising a first trench of a PMOS device and a second trench of an NMOS device, a high-k dielectric layer on a bottom and sidewalls of the trenches, a PMOS work function adjustment layer on the high-k dielectric layer in the first trench, an NMOS work function adjustment layer on the high-k dielectric layer in the second trench, and a metal electrode layer on the PMOS work function adjustment layer in the first trench and on the NMOS work function adjustment layer in the second trench.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 2, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jiaqi Yang, Jie Zhao
  • Patent number: 10672662
    Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The method includes providing a wafer. The wafer has a first surface and a second surface opposing to the first surface, and the wafer includes a plurality of first chip regions and a spacing region between adjacent first chip regions. The method also includes forming a first adhesive layer adhered to the second surface of the wafer, and forming an opening penetrating through the spacing region of the wafer and a plurality of first chips in the first chip regions on sides of the opening. Further, the method includes forming a molding layer in the opening. The molding layer covers a sidewall of the first chip and exposes a top surface of the first chip.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 2, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jian Gang Lu, Fu Cheng Chen