Patents Assigned to Semiconductor Manufacturing International (Shanghai) Corporation
  • Patent number: 11328994
    Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer on opposite sides of the metal interconnect line to expose a surface of the metal interconnect line and to form a recess; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer. The interconnect structure can prevent metal atoms of the metal interconnect line from diffusion into the first and second dielectric layers.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 10, 2022
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 11329054
    Abstract: A semiconductor device and a fabrication method are provided. The method includes providing a substrate; forming a first gate structure and source/drain doped layers over the substrate, where the source/drain doped layers are on both sides of the first gate structure; forming a dielectric layer covering the first gate structure and the source/drain doped layers over the substrate; forming a first trench exposing the first gate structure through the dielectric layer; forming a first conductive structure in the bottom region of the first trench; after forming the first conductive structure, forming an insulation layer in the top region of the first trench; using the insulation layer as a mask, forming recesses on source/drain doped layers through the dielectric layer on both sides of the insulation layer; and forming second conductive structures in the recesses.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11329055
    Abstract: Semiconductor cell and its forming method and operating method are provided. The semiconductor device includes: a substrate with a first region; a first nanopillar, formed on a substrate surface of the first region and perpendicular to the substrate surface; a first source/drain region, formed at a bottom of the first nanopillar and in a portion of the substrate in the first region; a first gate structure, surrounding the first nanopillar and formed on the first source/drain region; and a second source/drain region, formed at a top of the first nanopillar and on the first gate structure.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11329144
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region; forming a plurality of first initial fin structures on the first region of the semiconductor substrate; forming a dummy gate structure across the first initial fin structures by covering portions of top and sidewall surfaces of the first initial fin structures; forming a dielectric layer covering sidewall surfaces of the dummy gate structure and exposing a top surface of the dummy gate structure; removing the dummy gate structure to form a first opening in the dielectric layer and expose portions of top and sidewall surfaces of the first initial fin structures; and performing at least one trimming process on the first initial fin structures to form fin first structures. A width of each first fin structure is smaller than a width of each first initial fin structure.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Shiliang Ji
  • Patent number: 11328758
    Abstract: A magnetic memory and its programming control method and reading method, and a magnetic storage device of the magnetic memory are provided in the present disclosure. The magnetic memory includes a first magnetic tunnel junction memory cell, including a first terminal coupled to a first bit line, and further includes a switch device, including a first terminal coupled to a second terminal of the first magnetic tunnel junction memory cell, and a control terminal connected to a switch control signal. The magnetic memory further includes a second magnetic tunnel junction memory cell, including a first terminal coupled to a second bit line, and a second terminal coupled to a second terminal of the switch device. The magnetic memory further includes a first transistor, a second transistor, and a sensing amplifier.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Dan Ning, Zi Jian Zhao, Tao Wang, Hao Ni
  • Publication number: 20220139715
    Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 5, 2022
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Sue Chen
  • Patent number: 11322399
    Abstract: Semiconductor structure and method for forming the semiconductor structure are provided. An exemplary method includes: providing a substrate, including a first region and a second region; forming a gate structure over the substrate; forming a first interlayer dielectric layer over the substrate; forming a plurality of metal plugs in the first interlayer dielectric layer; forming a second interlayer dielectric layer over the first interlayer dielectric layer; forming a first via in the first region exposing a metal plug, and a second via in the second region exposing the first interlayer dielectric layer by etching the second interlayer dielectric layer; fully filling the first via with a first tungsten layer; forming an adhesion layer over the first tungsten layer, the second interlayer dielectric layer, and a sidewall and bottom of the second via; and fully filling the second via with a second tungsten layer.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 3, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Li Jiang
  • Patent number: 11322353
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a layer to-be-etched including a first sub-trench region and a second sub-trench region. The method also includes forming a first mask layer over the layer to-be-etched and a second mask layer over the first mask layer, and forming a first sub-trench disposed over the first sub-trench region in the second mask layer. In addition, the method includes forming a first divided trench in the first mask layer and forming a second sub-trench disposed over the second sub-trench region in the second mask layer. Further, the method includes forming a first divided filling layer in the first divided trench, and forming a first middle trench in the first mask layer. The first divided filling layer divides the first middle trench in a second direction.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 3, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jisong Jin, Zejun He, Jia Ni, Yanhua Wu, Junling Pang
  • Publication number: 20220130672
    Abstract: A semiconductor structure formation method and a mask are provided.
    Type: Application
    Filed: March 31, 2021
    Publication date: April 28, 2022
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong JIN
  • Patent number: 11315796
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a substrate having a first region, second regions and third regions; and forming a patterned structure on the substrate. The patterned structure includes at least one first patterned layer on the first region, at least one second patterned layer on the second region and at least one third patterned layer on the third region, the at least one first patterned layer is discrete from the at least one second region and the at least one second region is discrete from the at least one third region. The method also includes removing the second patterned layer; and etching the substrate using the first patterned layer and the third patterned layer as an etching mask to form a base substrate, the first fin on the base substrate and the third fin on the base substrate.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 26, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Publication number: 20220122947
    Abstract: A semiconductor structure and a forming method thereof are provided.
    Type: Application
    Filed: March 31, 2021
    Publication date: April 21, 2022
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong JIN
  • Patent number: 11309317
    Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a base substrate including a first region, a second region and a third region between the first and the second region; forming a dummy gate structure extending from the first region to the second region and through the third region; forming first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region; forming second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region; forming an opening in the dummy gate structure in the third region and exposing the base substrate in the third region; and forming an interlayer dielectric layer within the opening to have a top surface coplanar with the dummy gate structure.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11309182
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhao Junhong, Zhao Hai
  • Patent number: 11309318
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a semiconductor substrate including a first plug-cutting region and a fin-cutting region, and forming an initial to-be-cut fin partially extended to the fin-cutting region. The method also includes forming a gate structure across the initial to-be-cut fin, and forming a dielectric layer covering a sidewall of the gate structure and the initial to-be-cut fin. In addition, the method includes forming a cutting opening over the first plug-cutting region by removing a portion of the dielectric layer and a portion of the initial to-be-cut fin. A remaining initial to-be-cut fin forms a cutting fin. Further, the method includes forming a cutting structure in the cutting opening, and forming a first plug structure in a remaining dielectric layer. The cutting structure cuts the first plug structure in a width direction of the cutting fin.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Patent number: 11309891
    Abstract: The present application is directed to a level shifting circuit. In one form, a level shifting circuit includes a first inverter, a level shifting unit, and a fast driving unit. The first inverter is configured to invert an input signal received at an input node and to output an inverted input signal to a second input node. The level shifting unit is configured to perform amplitude up-shifting processing on a received input signal. The fast driving unit is configured to pull up an output signal of an output node of the level shifting unit by increasing a discharge current of the level shifting unit when receiving the input signal.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Guo Zhen Ye
  • Patent number: 11309184
    Abstract: A semiconductor structure and a formation method thereof are disclosed. The formation method includes: providing a base, wherein a first mandrel layer and a first mask layer located on the first mandrel layer are formed on the base, and openings exposing the first mandrel layer are formed in the first mask layer; forming a second mandrel layer covering the first mask layer, wherein the second mandrel layer also fills the openings; forming first trenches running through the second mandrel layer, the first mask layer and the first mandrel layer, wherein the side walls of the first trenches expose the second mandrel layer in the openings; forming side wall layers on the side walls of the first trenches; and etching to remove the second mandrel layer and the first mandrel layer below the positions of the openings by taking the side wall layers as masks to form second trenches running through the first mandrel layer, wherein the second trenches and the first trenches are isolated by the side wall layers.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wang Wei, Su Bo, Sun Linlin, He Qiyang
  • Patent number: 11309420
    Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate having fins and forming an initial gate structure across the fins, which covers a portion of a top surface and sidewall surfaces of the fins, and includes an initial first region and an initial second region on the initial first region. A bottom boundary of the initial second region is higher than the top surface of the fins, and a size of the initial first region is larger than a size of the initial second region. A first etching process is performed on sidewalls of the initial gate structure to form a gate structure, which includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region. A size of the first region is smaller than a size of the second region.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Bo Su
  • Patent number: 11309183
    Abstract: A semiconductor structure and a forming method thereof are provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jin Jisong
  • Patent number: 11309262
    Abstract: The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Dong Wang, Xiao Yan Bao, Tian Hua Dong, Guang Ning Li
  • Patent number: 11307502
    Abstract: Embodiments and implementations of the present disclosure provide assistant pattern configuration methods, masks and forming methods thereof, and related devices.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Feng Bai, Wanjuan Zhang, Yibin Huang, Yao Xu, Fan Zhang