Abstract: A method for forming a semiconductor structure includes providing an initial semiconductor structure formed in a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer to expose a portion of the initial semiconductor structure; etching the portion of the initial semiconductor structure exposed at a bottom of the first opening to form a second opening in the initial semiconductor structure; and forming a contact layer in the second opening and a third opening in the contact layer. The contact layer has a concave top surface, and the third opening is located above the concave top surface of the contact layer and under the first opening. The method further includes forming a conductive structure in the first opening and the third opening.

Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate; a gate structure on the substrate and extending along a first direction; source/drain doped layers in the substrate at sides of the gate structure; a first conductive structure on the source/drain doped layers; an opening at a top of the gate structure and the first conductive structure; and a second conductive structure in the opening. The opening extends along a second direction and the second direction is different from the first direction. The second conductive structure is insulated from the first conductive structure and in contact with the gate structure.

Abstract: Semiconductor devices are provided. An exemplary semiconductor device includes a semiconductor substrate having a first region. The first region includes a first middle region and a first edge region adjacent to and surrounding the first middle region; and a surface of the first middle region of the semiconductor substrate is higher than a surface of the first edge region of the semiconductor substrate. The semiconductor device also includes a plurality of first fins discretely formed on the first middle region of the semiconductor substrate; and an isolation structure formed on the first middle region of the semiconductor substrate and the first edge region of the semiconductor substrate and covering portions of sidewall surfaces of the first fins.

Abstract: A method for manufacturing semiconductor devices is provided. The method includes: providing a substrate structure comprising a semiconductor substrate and a trench insulator portion in the semiconductor substrate; forming a dummy gate on the semiconductor substrate; performing a first ion implantation into the semiconductor substrate to form a first doped region between the trench insulator portion and the dummy gate; and forming a first connecting member connecting the dummy gate with the first doped region.

Abstract: A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The semiconductor includes a substrate; a gate structure on the substrate; and a dielectric layer on the substrate and covering sidewall surfaces of the gate structure. The dielectric layer includes an opening passing through the gate structure along a direction perpendicular to an extending direction of the gate structure. The semiconductor structure also includes a first isolation layer in the opening and with a top surface lower than a top surface of the gate structure.

Abstract: Semiconductor device is provided. The semiconductor device includes a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region. A first work function layer is formed on the base substrate in the second region. A second work function layer is formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided.

Abstract: A semiconductor structure and a method for forming the same are provided in embodiments of the present disclosure. The forming method includes: providing a base; forming a trench in the base, and forming a first dielectric layer on the bottom surface and side walls of the trench; forming a conductor layer, the conductor layer covering the first dielectric layer on the bottom surface of the trench; forming a second dielectric layer in the trench on the conductor layer; and forming a drift region on a side, provided with the trench, of the base. The forming method can improve the breakdown voltage of an LDMOS device and also reduce the Ron of the LDMOS device, thereby improving the performance of the LDMOS device.

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are disclosed. One form a semiconductor structure includes: a substrate, comprising a first region used to form a well region and a second region used to form a drift region, wherein the first region is adjacent to the second region; and a fin, protruding out of the substrate, wherein the fins comprise first fins located at a junction of the first region and the second region and second fins located on the second region, and a quantity of the second fins is greater than a quantity of the first fins.

Abstract: Correction method of mask layout and mask containing corrected layout are provided. The method includes providing a target layout including a plurality of main patterns. Each main pattern includes a first side and an opposite second side. Extending directions of the first side and the second side are perpendicular to a first direction. Each main pattern also includes a third side and an opposite fourth side. Extension directions of the third side and the fourth side are perpendicular to a second direction. The second direction and the first direction are perpendicular to each other. The method also includes acquiring position information of each main pattern, and obtaining position information of auxiliary patterns adjacent to each main pattern. The method also includes, according to the position information of the auxiliary patterns adjacent to each main pattern, arranging the auxiliary patterns adjacent to each main pattern around each main pattern.

Abstract: A semiconductor structure and a forming method thereof are provided. In one form, a semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, where the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, where on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Abstract: A method for forming a semiconductor structure includes providing a substrate, forming a stop layer over a surface of the substrate, forming a dielectric layer over a surface of the stop layer, forming a first opening in the dielectric layer and exposing a portion of the stop layer, modifying the portion of the stop layer exposed at a bottom of the first opening to form a modification layer, and removing the modification layer to form a second opening from the first opening.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate, and forming a first core layer on the substrate. The substrate includes a pull-up transistor region. The method also includes forming separately arranged second core layers on the first core layer, and forming a first sacrificial sidewall spacer on a sidewall of a second core layer. A gap is formed between adjacent first sacrificial sidewall spacers over the pull-up transistor region. In addition, the method includes removing the second core layers, and then etching the first core layer using the first sacrificial sidewall spacers as a mask until the substrate is exposed. The gap is transferred to a region between adjacent etched first core layers over the pull-up transistor region. Further, after etching the first core layer, the method includes forming a dielectric layer to fully fill the gap.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate, a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins, a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region, an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region, and an N-region mask layer formed on sidewall surfaces of the N-type doped epitaxial layer and covering the P-type doped epitaxial layer. A portion of the N-type doped epitaxial layer exposed by the N-region mask layer is processed by an N-type dopant segregated Schottky doping process.

Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.