Abstract: A semiconductor device and a fabrication method of the semiconductor device are provided. The semiconductor device includes a substrate, and a dielectric layer disposed over the substrate. The dielectric layer contains a contact hole, and a bottom of the contact hole exposes a surface of the substrate. The semiconductor device also includes a metal silicide layer disposed on the surface of the substrate exposed by the bottom of the contact hole. Further, the semiconductor device includes a barrier layer disposed on a surface of the metal silicide layer, and a plug layer disposed over the barrier layer and fully filling the contact hole.

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a gate structure on the base substrate; source/drain doped layers in the base substrate on sides of the gate structure; a first dielectric layer on the base substrate and covering the source/drain doped layers; a mask layer on a top of the gate structure between the source/drain doped layers; a second dielectric layer on the first dielectric layer and exposing a surface of the mask layer; first grooves in the second dielectric layer and the first dielectric layer, and exposing the source/drain doped layers; a first conductive structure in each first groove; a second groove in the mask layer, and exposing the gate structure at a bottom of the second groove; and a spacer on sidewalls of the second groove.

Abstract: Semiconductor devices fabrication method is provided. The method for fabricating the semiconductor device includes: providing a semiconductor substrate; forming a gate structure on a surface of the semiconductor substrate; forming protective sidewall spacers on sidewall surfaces of the gate structure and to cover sidewall surfaces of the gate dielectric layer; forming sacrificial sidewall spacers on sidewall surfaces of the protective sidewall spacers and between the protective sidewall spacers and the gate structure; forming a first dielectric layer on the surface of the semiconductor substrate around the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; forming conductive plugs in the first dielectric layer at opposite sides of the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; and removing the sacrificial sidewall spacers to form air gap spacers between the protective sidewall spacers and the conductive plugs.

Abstract: Methods for forming a semiconductor structure are provided. In one form, a method includes: providing a base; forming an initial pattern layer on the base; and performing atomic layer etching processing on a sidewall of the initial pattern layer one or more times to form a pattern layer, where the atomic layer etching processing includes: forming an organic layer on the sidewall of the initial pattern layer; and removing the organic layer. Generally, bond energy between an atom on an outermost surface of the sidewall of the initial pattern layer and an atom at an inner layer is less than bond energy between the atom at the inner layer. The organic layer usually includes an element that may react with the sidewall of the initial pattern layer, further reducing the bond energy between the atom on the outermost surface of the sidewall of the initial pattern layer and the atom at the inner layer.

Abstract: A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate and a first metal layer in the substrate; forming a dielectric layer with a first opening exposing a portion of a top surface of the first metal layer on the substrate; bombarding the portion of the top surface of the first metal layer exposed by the first opening, by using a first sputtering treatment, to make metal materials on the top surface of the first metal layer be sputtered onto sidewalls of the first opening to form a first adhesion layer; and forming a second metal layer on a surface of the first adhesion layer and on the exposed portion of the top surface of the first metal layer using a first metal selective growth process.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer having a functional region and a non-functional region surrounding the functional region; a first dielectric layer formed on the wafer; a first opening formed in the first dielectric layer on the non-function region of the wafer; and a first connection layer formed in the first opening. The first connection layer closes a top portion of the first opening and a first void is formed in the first connection layer in the first opening.

Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.

Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate, a plurality of fins protruding from the semiconductor substrate, an isolation layer formed on the fins and with a bandgap greater than a bandgap of the fins, and a first channel layer formed on the isolation layer and isolated from the isolation layer.

Abstract: A method for forming a semiconductor device includes providing a to-be-etched layer, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of a first region, forming a sidewall spacer material layer on the core layer and the first mask layer, removing the sidewall spacer material layer on a top surface of the core layer, removing the core layer and the first mask layer at a bottom of the core layer to form a first trench, removing the sidewall spacer material layer on the first mask layer of a second region, forming a first patterned layer exposing the first mask layer of the second region, and using the first patterned layer as a mask to remove the first mask layer of the second region to form a second trench.

Abstract: A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.

Abstract: Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate and a gate structure on the substrate. The substrate contains source-drain openings on both sides of the gate structure. The semiconductor structure also includes a first stress layer formed in a source-drain opening of the source-drain openings. The first stress layer is doped with first ions. In addition, the semiconductor structure includes a protection layer over the first stress layer, and an inversion layer between the first stress layer and the protection layer. The protection layer is doped with second ions, and the inversion layer is doped with third ions. A conductivity type of the third ions is opposite to a conductivity type of the second ions.

Abstract: Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate and a dummy gate structure on the substrate. The substrate contains source-drain openings on both sides of the dummy gate structure. The semiconductor structure also includes a first stress layer formed on a sidewall of a source-drain opening of the source-drain openings. Further, the semiconductor structure includes a second stress layer formed at a bottom of the source-drain opening and on the first stress layer. The second stress layer fully fills the source-drain opening, and stress of the first stress layer is less than stress of the second stress layer.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.