Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.

Abstract: A semiconductor structure and a method for forming same are provided, the forming method including: providing a base including a plurality of adjacent device unit regions, an initial device gate structure spanning a plurality of device unit regions being formed on the base; etching a portion of the initial device gate structure in thickness at a junction between the adjacent device unit regions to form a top opening; forming a spacer layer on a side wall of the top opening; etching a remainder of the initial device gate structure exposed from the spacer layer, and forming a bottom opening exposed from the base within the remainder of the initial device gate structure, the remainder of the initial device gate structure being used as a device gate structure; and forming an isolation structure within the top opening and the bottom opening. The spacer layer is configured to adjust a width of the bottom opening, so that the width of the bottom opening is less than a width of the top opening.

Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a semiconductor substrate; forming initial fins on the semiconductor substrate; forming a gate structure material layer on the semiconductor substrate and the initial fins, the gate material layer having a top surface higher than the initial fins; forming a trench in the gate structure material layer and the initial fins, which passes through the initial fins along a direction perpendicular to an extending direction of initial fins and in parallel with a surface of the semiconductor substrate to form initial fins into fins; forming an isolation layer in the trench having a top surface higher than the fins; and forming gate structures on both sides of the isolation layer by etching the gate structure material layer.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same.

Abstract: A semiconductor structure and a method for forming the same, and a transistor are provided. In one form, a method includes: providing a base, where a dummy gate layer is formed on the base, a spacer is formed on a side wall of the dummy gate layer, an interlayer dielectric layer is formed on the base exposed from the dummy gate layer and the spacer, and the interlayer dielectric layer exposes a top of the dummy gate layer and a top of the spacer; removing a portion of a height of the dummy gate layer to form a remaining dummy gate layer, where the remaining dummy gate layer and the spacer enclose a trench; thinning a spacer exposed from the remaining dummy gate layer along a direction perpendicular to a side wall of the trench; after the thinning, removing the remaining dummy gate layer to form a gate opening within the interlayer dielectric layer; and forming a metal gate structure in the gate opening. Through the thinning, a gate opening whose side wall is provided with a remaining spacer is T-shaped.

Abstract: A photolithography process includes providing a first test layout including test patterns, and a first light source; forming an initial mask layout according to the first test layout; forming a mask layout including mask layout patterns through an optical proximity correction or a phase-shifting masking; forming exposed patterns by exposing the mask layout using the first light source; and determining a weak region from the first test layout. A first distance between adjacent test patterns in the weak region is unequal to a second distance between corresponding exposed patterns. The photolithography process further includes performing a re-layout on the weak region to increase the first distance, thereby providing an adjusted test layout; performing a light-source optimization to obtain an adjusted light source; and determining the adjusted test layout and the adjusted light source as a second test layout and a second light source, respectively when process window requirements are satisfied.

Abstract: A method for detecting heat generated by a semiconductor device including a first MOS device and an active device on a substrate is provided. The method includes obtaining a first curve of a performance parameter of the first MOS device as a function of temperature when the active device is not operating, obtaining a second curve of the performance parameter of the first MOS device as a function of temperature when the active device is operating, and obtaining a heat generating condition of the active device according to a degree of deviation between the first curve and the second curve.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate including a high-frequency-block group and a low-power-block group; high-frequency-type logic standard cells located on the high-frequency-block group, and having a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; low-power-type logic standard cells located on the low-power-block group, and having a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power. The high-frequency-type cell height is higher than the low-power-type cell height. The high-frequency-type operating frequency is greater than the low-power-type operating frequency. The high-frequency-type power is greater than the low-power-type power. The high-frequency-type logic standard cells include high-frequency-type fins, and the low-power-type logic standard cells include low-power-type fins.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type opposite the first conductivity type, the first region and the second region being adjacent to each other and forming a pn junction in the semiconductor substrate, a semiconductor fin on the semiconductor substrate, and an electrode on the semiconductor fin. The pn junction in the semiconductor substrate has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device.

Abstract: A method for fabricating a semiconductor structure includes providing a base substrate; and forming two first fin structures and an initial isolation structure. The initial isolation structure includes a first region, located between the two first fin structures, and two second regions, each separated from the first region by a first fin structure. The method includes implanting doping ions into the initial isolation structure in the first region; and forming an isolation structure by removing a portion of the initial isolation structure. The removal rate of the initial isolation structure formed in the first region is smaller than the removal rate of the initial isolation structure formed in the two second regions. The top surface of the isolation structure is higher in the first region than in the two second regions. The method further includes forming a plurality of source/drain openings by removing a portion of the first fin structures.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate. The base substrate includes a plurality of non-device regions. The method also includes forming a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions. In addition, the method includes forming a first barrier layer on sidewalls of the edge fin. Further, the method includes forming an isolation material layer over the base substrate, over a top of the edge fin, over sidewall and top surfaces of the middle fin structure, and over sidewalls of the first barrier layer. The isolation material layer has a material density smaller than the first barrier layer.

Abstract: Semiconductor device is provided. The semiconductor device includes a base substrate and a first dielectric layer on the base substrate. The first dielectric layer contains a first trench and a second trench passing therethrough, and a width of the second trench is larger than a width of the first trench. The semiconductor device further includes a first gate dielectric layer and a first gate electrode in the first trench. A first recess is on the first gate dielectric layer between the first gate electrode and the first dielectric layer. The semiconductor device further includes a second gate dielectric layer and a second gate electrode in the second trench. A second recess is on the second gate dielectric layer between the second gate electrode and the first dielectric layer. The semiconductor device further includes a first protection layer in the first recess and a second protection layer in the second recess.

Abstract: SAR-DAC devices and operation methods of SAR-DAC devices are provided. An exemplary SAR-DAC device includes a comparator having a positive input terminal and a negative input terminal; and a DAC core unit including a first capacitor, a second capacitor, and a current-controlled discharging structure. The first capacitor includes a first charging-discharging terminal. The second capacitor includes a second charging-discharging terminal. The current-controlled discharging structure includes current beam circuit units. Each current beam circuit unit includes a first discharging input terminal connected to the first charging-discharging terminal and a second discharging input terminal connected to the second charging-discharging terminal.

Abstract: Semiconductor structure and fabrication method are provided. An exemplary method includes: providing a to-be-etched layer; forming a first mask material layer with a barrier region on the to-be-etched layer; forming a first mask groove and a second mask groove separated from each other in the first mask material layer and exposing two sidewalls of the barrier region along an extending direction of the first mask groove; forming barrier layers on exposed sidewalls of the barrier region; forming a first mask through hole in the barrier region of the first mask material layer by etching a portion of the barrier region of the first mask material layer by using the barrier layers as a mask; and forming a first groove, a second groove, and a through hole, by etching the to-be-etched layer using the barrier layers and the first mask material layer as a mask.

Abstract: A semiconductor structure and a method for forming same are provided, the method including: providing a base including a substrate and a fin protruding from the substrate, the substrate including a P-type logic region and a pull up transistor region; forming a gate layer across the fin; forming a mask spacer covering a side wall of a fin in the pull up transistor region and a side wall of a portion of a fin in the P-type logic region; removing a portion of thicknesses of the fins on both sides of the gate layer using the mask spacer as a mask, to form a groove enclosed by the fin and the mask spacer in the P-type logic region and a straight slot penetrating the fin and the mask spacer in the pull up transistor region along a direction perpendicular to the side wall of the fin; and forming a P-type source/drain doped layer in the groove and the straight slot.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region.