Abstract: A semiconductor structure and a method for forming same are provided.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, a dummy gate structure being formed on the base, a source/drain doping region being formed in the base on both sides of the dummy gate structure, a dielectric layer being formed on the base exposed by the dummy gate structure, and the dielectric layer covering the source/drain doping region; etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region; forming a contact plug in the contact hole, the contact plug being electrically connected to the source/drain doping region; after forming the contact plug, removing the dummy gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening. Embodiments of the present disclosure are advantageous to simplify process complexity and increase process windows.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: A semiconductor structure and a method for forming same are provided, the method including: providing a base including a substrate and a fin protruding from the substrate, the substrate including a P-type logic region and a pull up transistor region; forming a gate layer across the fin; forming a mask spacer covering a side wall of a fin in the pull up transistor region and a side wall of a portion of a fin in the P-type logic region; removing a portion of thicknesses of the fins on both sides of the gate layer using the mask spacer as a mask, to form a groove enclosed by the fin and the mask spacer in the P-type logic region and a straight slot penetrating the fin and the mask spacer in the pull up transistor region along a direction perpendicular to the side wall of the fin; and forming a P-type source/drain doped layer in the groove and the straight slot.

Abstract: Semiconductor structures are provided. An exemplary semiconductor structure includes a semiconductor substrate having a first region and a second region and a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region. A first oxide layer is on side surfaces of the plurality of first fins; and a second oxide layer is on side surfaces of the second fins. A corner between a top surface and a side surface of each first fin is a first rounded corner. A corner between a top surface and a side surface of each second fin is a second rounded corner. A radius of curvature of the first rounded corner is different from a radius of curvature of the second corner.

Abstract: A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins.

Abstract: A semiconductor structure and a formation method thereof are provided. A form of the formation method of the semiconductor structure includes: providing a substrate; forming a dielectric layer on the substrate; forming a contact hole in the dielectric layer; forming a seed layer on a bottom and a sidewall of the contact hole, where a thickness of the seed layer on the bottom of the contact hole is greater than a thickness of the seed layer on the sidewall of the contact hole; and forming a conductive plug in the contact hole. The semiconductor structure includes: a substrate; a dielectric layer located on the substrate; a contact hole located in the dielectric layer; a seed layer located on a bottom and a sidewall of the contact hole, where a thickness of the seed layer on the bottom of the contact hole is greater than a thickness of the seed layer on the sidewall of the contact hole; and a conductive plug located in the contact hole.

Abstract: Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.

Abstract: Method for fabricating an insulated gate bipolar transistor (IGBT) is provided. A substrate includes a device region, that includes control regions and turn-off regions, arranged alternately. A drift region is formed in the substrate. A well region is formed in a portion of the substrate in the control regions and the turn-off regions, and first gate structures are formed in the control regions. The well region is in contact with the drift region, and the first gate structures are in contact with both the drift region and the well region. Emission regions are formed in the well region of the control regions and in the substrate on one or both sides of each first gate structure, the drift region and each emission region are separated by the well region, and the emission regions are electrically connected to a portion of the well region in the turn-off region.

Abstract: The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region.

Abstract: Anti-fuse structure circuit and method of forming an anti-fuse structure circuit are provided. A substrate is provided, and an anti-fuse is formed on the substrate by forming a first gate structure and a dielectric layer on the substrate and forming conductive plugs respectively in the dielectric layer at two sides of the first gate structure. The dielectric layer covers the first gate structure, and the conductive plugs have a width decreasing from top to bottom. A second gate structure is formed on the substrate. A top surface of the first gate structure is higher than a top surface of the second gate structure. The dielectric layer also covers the second gate structure. The conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least a first region; forming a dielectric structure over the semiconductor substrate; forming a plurality of first openings in the dielectric structure in the first region by removing portions of the dielectric structure in the first region; forming a first barrier member in each of the plurality of first openings; forming second openings with sidewall surfaces exposing sidewall surfaces of the first barrier members by removing portions of the dielectric structure between adjacent first openings; and forming a second barrier member in each of the plurality of second openings.

Abstract: A semiconductor device and fabrication method thereof are provided. The fabrication method include: providing a to-be-etched material layer; forming a plurality of discrete sacrificial layers on the to-be-etched material layer; forming first initial spacers on sidewalls of each sacrificial layer, where each first initial spacer includes a first bottom region and a first top region on the first bottom region; removing the sacrificial layers; removing the first bottom region of the first initial spacer to form a first spacer from the first top region; forming second spacers on sidewalls of each first spacer; removing the first spacer; and etching the to-be-etched material layer by using the second spacers as an etch mask.

Abstract: Methods for fabricating a transistor and an electro-static discharge (ESD) device are provided. In a method, a first well area doped with a first well ion is formed in a base substrate. A second well area is doped with a second well ion in the base substrate. The second well area includes a first region adjacent to the first well area. A first ion doping region doped with first ions is formed in the first well area and the first region. A type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. A gate structure is formed on a part of the first well area and at least a part of the first region.

Abstract: A microphone and its manufacturing method, relating to semiconductor techniques. The microphone comprises a substrate with a back through-hole going through the substrate; a first electrode layer on the substrate covering the back through-hole; a back plate on the substrate, wherein the back plate and the first electrode layer form a cavity, and the first electrode layer comprises a gap connecting the back through-hole and the cavity; and a second electrode layer in the cavity and on a bottom surface of the back plate. In this inventive concept, the gap in the first electrode layer increases the sensitivity of the first electrode layer and thus improves the Signal-to-Noise Ratio (SNR).

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate structures, a source/drain doped layer, a barrier layer, and a dielectric layer on a base substrate. The barrier layer covers the entire top surfaces of the plurality of gate structures. The dielectric layer covers the source/drain doped layer, the barrier layer, and the gate structures. The method further includes forming a plurality of first vias in the dielectric layer on both sides of each gate structure above the source/drain doped layer; forming a plurality of second vias on the gate structures to expose the barrier layer; performing a pre-amorphizing implantation process on the surface of the source/drain doped layer at the bottom of the first vias; removing the barrier layer at the bottom of the second vias; and forming a metal silicide layer on the surface of the source/drain doped layer through a metal silicidation process.

Abstract: A method for fabricating an SRAM includes forming a plurality of first fin structures, a plurality of second fin structures, and an isolation layer. Each first fin structure is adjacent to a second fin structure and includes a first replacement region exposed by the isolation layer. The method includes forming pull down (PD) transistors, including forming PD gate structures to partially cover the first fin structures; forming a fin sidewall film on sidewall surfaces of each first replacement region; forming a first PD dielectric layer, exposing each first replacement region, to cover sidewall surfaces of the fin sidewall film; removing the first replacement region and the fin sidewall film on sidewall surfaces of the first replacement region; and forming a first source/drain doped layer. The method also includes forming adjacent transistors, including forming a second source/drain doped layer in the second fin structures adjacent to the first source/drain doped layer.

Abstract: A semiconductor device includes a base substrate; a plurality of doped regions formed in the base substrate; and a target capping layer formed on surfaces of the doped regions. The target capping layer includes a silicide region and a non-silicide region surrounding the silicide region, and the silicide region has a reduced thickness compared with a thickness of the non-silicide region. The semiconductor device further includes a metal silicide layer formed in the silicide region of the target capping layer and having the reduced thickness; a dielectric layer formed on the target capping layer and the base substrate; and a plurality of vias formed in the dielectric layer and connected to the metal silicide layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.