Abstract: A method of manufacturing a semiconductor device includes providing a substrate having first and second semiconductor fins, forming an insulating layer on the substrate having first and second recesses exposing a portion of the respective first and second semiconductor fins, forming a gate dielectric layer on the first and second recesses and the exposed portions of the first and second semiconductor fins, forming a first work function adjustment layer on the gate dielectric layer, forming a functional layer on the first function adjustment layer, and forming first and second gates on portions of the functional layer of the respective first and second semiconductor fins. The opening area of the first recess is larger than the opening area of the second recess. The thickness of the functional layer on the first semiconductor fin is greater than the thickness of the functional layer on the second semiconductor fin.

Abstract: A power supply circuit, its generating and control methods are presented, relating to smart wearable devices. The power supply circuit comprises a Bandgap voltage reference, a real-time detection and control circuit, and a substitute voltage source. The real-time detection and control circuit is connected to the Bandgap voltage reference and the substitute voltage source, and adjusts an output voltage of the substitute voltage source to match an output voltage of the Bandgap voltage reference. After these output voltages are equal, the output voltage of the power supply circuit is provided by the substitute voltage source, and the Bandgap voltage reference can be disconnected from the circuit. This circuit can lower the power consumption of the Bandgap voltage reference without affecting the stability of the voltage output.

Abstract: A 3-D flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two sides of the fin structure, with the first gate layer being surrounded by the first, the second and the third insulation layers, and at least one channel layer covering the fin structure and the third insulation layer; and forming a groove by etching the channel layer, the second insulation layer and the first gate layer along an extension direction of the fin structure. This inventive concept improves the storage density of a 3-D flash memory device.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a semiconductor structure, where the semiconductor structure includes an active region and a gate structure located in the active region, the gate structure at least including a gate electrode, and the active region exposing an upper surface of the gate electrode; forming a surface insulator layer on the upper surface of the gate electrode; forming a patterned interlayer dielectric layer on the semiconductor structure, where the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and forming a conductive contact layer passing through the first through hole and contacting with the active region.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.

Abstract: A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

Abstract: A method for forming a semiconductor device includes providing a substrate, the substrate including a first trench in an NMOS region and a second trench in a PMOS region. The method also includes depositing a high-K dielectric layer, a cap layer, and a P-type work function metal layer on the bottom and side walls of the first trench and the second trench, removing the P-type work function metal layer and the cap layer from the bottom and sidewalls of the first trench, depositing an N-type work function metal layer on the high-K dielectric layer in the first trench and on the P-type work function metal layer in the second trench, and depositing a metal electrode layer on the N-type work function metal layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.

Abstract: A photomask manufacturing method relating to semiconductor technology is presented. The manufacturing method involves providing a substrate structure comprising an etch material layer, a first sacrificial layer on a portion of the etch material layer, and a photomask layer on an upper surface of the etch material layer and on an upper surface and a side surface of the first sacrificial layer; forming a second sacrificial layer covering the photomask layer on the etch material layer and on the side surface of the first sacrificial layer; etching the photomask layer not covered by the second sacrificial layer to expose the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and removing the photomask layer on the etch material layer. This photomask manufacturing method offers a photomask of better symmetricity than those from conventional methods.

Abstract: A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a scattering bar by an optical proximity correction process; and providing a semiconductor substrate having a first dielectric layer and at least one conductive via. The method also includes aligning the reticle with the semiconductor substrate with the conductive via to align the scattering bar next to the conductive via; and forming metal line patterns on the first dielectric layer and a top surface of the conductive via to completely cover the conducive via.

Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a base substrate with a bottom metallic layer in the base substrate and a dielectric layer on the base substrate; forming interconnect openings through the dielectric layer and exposing the bottom metallic layer, where each interconnect openings includes a contacting hole and a groove on the contacting hole; forming a first conducting layer in the contacting hole, where the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and after forming the first conducting layer, forming a second conducting layer in the groove, where the second conducting layer is made of a material having a second conductivity along a direction parallel to the top surface of the base substrate and the first conductivity is greater than the second conductivity.

Abstract: A balun structure is provided. The balun structure includes a substrate, a first coil structure and a second coil structure having a spiral shape and on the substrate. The first coil structure includes a first single-layer coil surrounding by first laminated coils that are connected to the first single-layer coil. The second coil structure can include a second single-layer coil and second laminated coils that are connected to the second single-layer coil. A projection of the first single-layer coil and a projection of the second single-layer coil on a surface of the substrate overlap with each other. A number of the second laminated coils is larger than or equal to a number of the first laminated coils. The second laminated coils are arranged alternately with the first laminated coils or the first single-layer coil in a plane parallel to the surface of the substrate.

Abstract: A frequency divider circuit and a frequency synthesizer circuit are presented, comprising: first and second flip-flops; a phase inverter, wherein an output electrode of the first flip-flop is connected to an input electrode of the second flip-flop and an output electrode of the phase inverter, an output electrode of the second flip-flop is connected to an input electrode of the phase inverter and an input electrode of the first flip-flop, a control electrode of the phase inverter is connected to a control signal; and a control module, wherein the first flip-flop is connected to a voltage source through the control module, the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source. When the control signal is a first-mode signal, the first flip-flop is disconnected from the voltage source, providing a functionality of a N-division frequency divider.

Abstract: A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a semiconductor fin on the substrate, and an isolation region on opposite sides of the semiconductor fin, the isolation region having an upper surface substantially flush with an upper surface of the at least one semiconductor fin. The method also includes implanting ions into the substrate structure to form a doped region in the semiconductor fin and in the isolation region, etching back the isolation region to expose a portion of the semiconductor fin, and performing an annealing process to activate the implanted ions in the doped region. Because the annealing is performed after the etching back of the isolation region, a portion of the implanted ions diffuses out of the isolation region and the fin, thereby reducing ion diffusion into the channel region and improving the device performance.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a semiconductor substrate and a plurality of fins on the semiconductor substrate; forming an isolation structure on the semiconductor substrate, between adjacent fins and with a top surface lower than the top surfaces of the fins; forming a gate structure across of the fins by covering portions of top and side surfaces of the fins; forming a sidewall material layer to cover the gate structure and the fins; etching the sidewall material layer to form gate sidewall spacers on side surfaces of the gate structure and shadowing sidewall spacers on portions of side surfaces of the fins adjacent to the isolation structure; and performing an ion implantation process on the fins using the gate sidewall spacers and the shadowing sidewall spacers as a mask to form lightly doped regions in the fins.

Abstract: Fin field-effect transistors and fabrication methods are provided. An exemplary fabrication method includes providing a providing a plurality of fins on a surface of a semiconductor substrate; forming a gate structure across the fins by covering portions of top and side surfaces of the fins, wherein portions of the fins under the gate structure are channel regions; forming lightly doped regions in the fins at both sides of the gate structure by performing a lightly doping ion implantation process; performing a counter doping ion implantation process on a portion of each lightly doped region away from the channel region to form a counter doped region in the lightly doped region; and performing a source/drain doping process on the fins at both sides of the gate structure to form doped source/drain regions.

Abstract: MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure.

Abstract: A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.