Abstract: A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.

Abstract: A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole. This semiconductor interconnect structure provides improved reliability over conventional structures.

Abstract: Retention voltage generation circuits and electronic apparatus are provided.

Abstract: An electromechanical device may include a first substrate, a second substrate, a connector, and a protector. The connector may be formed of a first dielectric material and may be positioned between the first substrate and the second substrate. A first side of the connector may directly contact the first substrate. The protector may be formed of a second dielectric material and may directly contact a second side of the connector.

Abstract: Fin field-effect transistors (FinFETs) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having a plurality of fins; forming gate structures over the base substrate; forming a photoresist film having a plurality of exposure regions and non-exposure regions over the base substrate, the fins and the gate structures, wherein the exposure regions have first regions above the top surfaces of the gate structures and second regions below the top surfaces of the gate structures; performing an exposure process to the photoresist film; performing a post-baking process to cause photoacid in the second regions of the exposure regions to diffuse into portions of the photoresist film below the top surfaces of the gate structures in the non-exposure regions; developing exposed photoresist film to form photoresist layers; and performing a function doping process to the fins using the photoresist layers as a mask.

Abstract: A device includes a first integrated circuit containing a photodiode and a first metal interconnect structure connected to the photodiode, and a second integrated circuit containing a transistor and a second metal interconnect structure connected to the transistor. The first integrated circuit and the second integrated circuit are connected together through the first metal interconnect structure and the second metal interconnect structure. Since no transistor is present around the photodiode, the photodiode has an increased photosensitive area and an improved fill factor, resulting in an increase of the quantum efficiency, higher integration and lower consumption of the image sensor.

Abstract: A Fin-FET device and its fabrication method are provided. The method for fabricating the Fin-FET device includes forming a plurality of fin structures on a substrate, forming an isolation film on the substrate between neighboring fin structures, removing a portion of the isolation film to form an initial isolation layer with a top surface of the initial isolation layer lower than top surfaces of the fin structures, and implanting doping ions into the initial isolation layer. Further, the method also includes removing a portion of the initial isolation layer to form an isolation layer.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a core region of a substrate and a plurality of second fin structures in a peripheral region of the substrate, forming a first dummy gate structure including a first dummy gate oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second gate oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate electrode layer, performing an ion implantation process to tune the threshold voltages of the first fin structures, and removing each first dummy gate oxide layer. The method also includes removing each second dummy gate electrode layer, and forming a gate dielectric layer and a metal layer on each first fin structure and each second fin structure.

Abstract: A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an NMOS region and a PMOS region; forming a first high-K gate dielectric layer on the NMOS region of the substrate; forming an interfacial layer on the PMOS region of the substrate; forming a second high-K gate dielectric layer on the interfacial layer and the first high-K gate dielectric layer; forming a metal layer on the second high-K gate dielectric layer.

Abstract: A method for testing inter-layer connections is presented. The method entails: providing a test semiconductor device, wherein the test semiconductor device comprises a two-port resistance network; measuring base input resistances on at least one of the first and the second ports of the test semiconductor device for different numbers of resistance links in a defect-free circumstance; obtaining a correspondence relationship between the number of resistance links and the base input resistances; measuring actual input resistances on at least one of the first and the second ports of the test semiconductor device; and determining a position of the resistance link corresponding to the actual input resistances based on the correspondence relationship, wherein the position of the resistance link determines the location of a defect. This method can promptly locate a defect in inter-layer components and can reduce test time and simplify test procedures.

Abstract: A method for forming a semiconductor device includes forming a first insulator layer on a first substrate of a first semiconductor material, implanting hydrogen ions into the first substrate to form a hydrogen-implanted layer, forming a recessed region in the first substrate, forming a second semiconductor material in the recessed region, and forming a second insulator layer over the second semiconductor material and the first substrate. The method also includes providing a second substrate with a third insulator layer disposed thereon, bonding the first substrate with the second substrate, and removing a lower portion of the first substrate at the hydrogen-implanted layer. A portion of the first substrate is removed to expose a surface of the second semiconductor material in the recessed region, thereby providing a layer of the first semiconductor material adjacent to a layer of the second semiconductor material on the second insulator layer.

Abstract: A method for optimizing manufacturability of standard cells includes generating random contexts for the standard cells, inserting vias into the standard cells, and performing a lithography verification on the standard cells after the vias have been inserted. The method enables early detection and resolution of potential hot spots on standard cell pin connections and reduction of hot spots that are introduced by the router at the chip level. The early detection and reduction of hot spots shortens the cycle time of a standard-cell based design.

Abstract: A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Abstract: A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region. The method also includes forming a gate structure on each fin; and forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region. In addition, the method includes forming a first pull-down doped region connected to an adjacent pull-up doped epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region. Further, the method includes forming a second pull-down doped region by performing an ion-doped non-epitaxial layer process on the fin on another side of the gate structure in the pull-down transistor region.

Abstract: A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask.

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the semiconductor substrate, and forming a seal ring structure surrounding each of the IC devices. Forming the seal ring structure includes forming a plurality of interlayer dielectric layers on the semiconductor substrate, and forming a plurality of hollow through-hole structures within each of the interlayer dielectric layers.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.

Abstract: An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage.

Abstract: A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.