Abstract: A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

Abstract: A fabrication method of a semiconductor structure is provided. The method includes: providing a substrate; forming fin structures on the substrate along a first direction with isolation grooves between adjacent fin structures, where each fin structure includes sacrificial layers stacked along a normal direction of the substrate and a channel layer between every two adjacent sacrificial layers; forming a first isolation layer in each isolation groove; forming a second isolation layer at a surface of each first isolation layer to fill up a corresponding isolation groove; forming a dummy gate structure; removing first isolation layers; removing the dummy gate structure to form a gate opening at ends of the sacrificial layers along a second direction perpendicular to the first direction; removing the sacrificial layers to form gate grooves between adjacent channel layers; and forming a gate structure in the gate opening and the gate grooves surrounding the channel layers.

Abstract: A semiconductor structure and a formation method thereof are provided. One form of the formation method includes: providing a substrate; forming a plurality of discrete mandrel layers on the substrate, wherein a minimum pitch between mandrel layers of the plurality of mandrel layers is a second pitch, and a minimum pitch between each of other pitches is a first pitch; forming second side wall covering layer between the mandrel layers having the second pitch; removing a first side wall covering layer, and maintaining the second side wall covering layer; forming a third side wall covering layer on an exposed side wall of the mandrel layer; removing the mandrel layer and the second side wall covering layer; and etching the substrate by using the third side wall covering layer as a mask to form a desired pattern. In embodiments and implementations of the present disclosure, the mandrel layer and the second side wall covering layer are configured to define a pitch between the third side wall covering layers.

Abstract: A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a to-be-etched layer having a plurality of first regions and second regions; forming a first mask layer on the to-be-etched layer; doping portions of the first mask layer outside the second trench regions; forming a second mask layer on the first mask layer; forming a first trench penetrating the first mask layer and the second mask layer over the first regions; forming a mask sidewall spacer on sidewall surfaces of the first trench; removing the second mask layer; and removing the first mask layer in the second trench regions using the mask sidewall spacers and the doped portions of the first mask layer as an etching mask to form seconds trenches over the second trench regions of the plurality of second regions. The sidewall surface of the second trench exposes a corresponding mask sidewall spacer.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type opposite the first conductivity type, the first region and the second region being adjacent to each other and forming a pn junction in the semiconductor substrate, a semiconductor fin on the semiconductor substrate, and an electrode on the semiconductor fin. The pn junction in the semiconductor substrate has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a substrate including a first region and a second region, and forming a plurality of fins over the first region. The method also includes forming an isolation layer over a front surface of the substrate, and forming a power rail opening by etching the isolation layer and a first portion of the second region. In addition, the method includes forming a through-hole by etching a second portion of the substrate, and forming a first metal layer in the power rail opening and the through-hole. Further, the method includes thinning a back surface of the substrate until the first metal layer is exposed, and back-etching the back surface of the substrate to enable a back surface of the first metal layer to be above the back surface of the substrate.

Abstract: A method for fabricating a semiconductor device includes providing a to-be-etched layer, including alternately arranged first regions and second regions in a first direction. Each first region adjoins adjacent second regions, and each second region includes a trench region. The method includes forming a first mask layer on the to-be-etched layer; implanting doping ions into the first mask layer outside of the trench region; forming a doped separation layer in the first mask layer of the second region to divide the first mask layer into portions arranged in a second direction perpendicular to the first direction; forming a first trench in the first mask layer of the first region; and removing the first mask layer formed in the trench region on both sides of the doped separation layer to form a second trench divided into portions arranged in the second direction by the doped separation layer.

Abstract: A mask pattern, a semiconductor structure and a method for forming the semiconductor structure are provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.

Abstract: A method for fabricating a capacitor device includes providing a substrate; forming a first-layer electrode on the substrate; and forming a conductive layer on the first-layer electrode. The roughness of the first-layer electrode is a first roughness, the roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness. The method further includes forming a dielectric layer on the conductive layer; and forming a second-layer electrode on the dielectric layer. According to the disclosed method and capacitor device, by forming the conductive layer on the first-layer electrode, the roughness of the bottom electrode of the capacitor device is reduced, which effectively reduces the presence of protrusions on the surface of the bottom electrode. Therefore, the breakdown electric voltage of the capacitor device may be improved, and leakage current may be avoided. As such, the reliability of the capacitor device may be improved.

Abstract: A semiconductor structure and a method for forming same are provided. One form of the forming method includes: providing a base, the base including: a substrate and a channel stack on the substrate, the channel stack including a first channel layer and a second channel layer located on the first channel layer, the first channel layer and the second channel layer being made of different materials, and a first region and a second region, where the channel stack is located in the first region and the second region; forming an interlayer dielectric layer on the substrate exposed from the channel stack, where a gate opening from which the channel stack is exposed is formed in the interlayer dielectric layer; removing the second channel layer of the first region in the gate opening; removing the first channel layer of the second region in the gate opening; and forming a gate structure surrounding a remainder of the first channel layer and the second channel layer.

Abstract: An electrostatic discharge protection structure includes a laterally diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes an embedded bipolar junction transistor. A gate, a source, a buried layer lead-out area, and a substrate lead-out area of the LDMOS device are grounded. A drain and a body region lead-out area of the LDMOS device are electrically connected to a pad input/output terminal. In an embodiment, the embedded bipolar junction transistor includes a PNP transistor operative to transmit a reverse electrostatic discharge current. An N+ drain, a gate, an N+ source, and a P+ substrate lead-out area form a grounded-gate NMOS (GGNMOS) operative to transmit a forward electrostatic discharge current.

Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a semiconductor substrate having a dielectric structure and having at least a first region; a plurality of first openings formed in the dielectric structure in the first region; a first barrier member formed in each of the plurality of the first openings; a plurality of second openings formed between adjacent first barrier members and with sidewall surfaces exposing sidewall surfaces of the first barrier members; and a second barrier member formed in each of the plurality second openings.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method includes: providing a substrate, the substate having a first opening; forming a first epitaxial layer in the first opening, the first epitaxial layer having a second opening; forming a stop layer on sidewall surfaces and a bottom surface of the second opening; forming a second epitaxial layer on a top surface of the stop layer; after forming the second epitaxial layer, forming a dielectric layer on the substrate, the dielectric layer having a third opening exposing a surface of the second epitaxial layer; forming a fourth opening in the second epitaxial layer by etching the second epitaxial layer exposed by the third opening until the stop layer is exposed; and forming a contact layer on sidewall surfaces and a bottom surface of the fourth opening by performing a semiconductor metallization process.

Abstract: Method and system for monitoring a polishing pad is provided. The polishing pad includes a bottom layer, a polishing layer disposed on the bottom layer, and a plurality of mark structures disposed on the bottom layer and in the polishing layer to have a top surface coplanar with the polishing layer to indicate consumption level of the polishing layer. The monitoring system includes an acquisition module, a memory module, and a determining module connected to both the acquisition module and the memory module. The determining module, the acquisition module, and the memory module are configured to monitor the consumption level of the polishing layer and to recognize that the polishing pad needs to be replaced.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. One form of a forming method includes: providing a base; forming a plurality of discrete mandrel layers on the base, where an extending direction of the mandrel layers is a first direction, and a direction perpendicular to the first direction is a second direction; forming a plurality of spacer layers covering side walls of the mandrel layers; forming a pattern transfer layer on the base, where the pattern transfer layer covers side walls of the spacer layers; forming a first trench in the pattern transfer layer between adjacent spacer layers in the second direction; removing a mandrel layer to form a second trench after the first trench is formed; and etching the base along the first trench and the second trench to form a target pattern by using the pattern transfer layer and the spacer layer as a mask. In the present disclosure, the accuracy of the pattern transfer is improved.

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: Semiconductor cell structure and forming method thereof are provided. The semiconductor cell structure includes: a substrate including a first section and third regions on both sides of the first section in a first direction; and a first gate structure group including one or more first gate structures on the substrate. The first section includes a first region and a second region aligned along the first direction in the first section. The first region and the second region are configured to form transistors have a type opposite to a type of transistors configured to be formed in the third regions. The one or more first gate structures extend along the first direction across the first region, the second region, and the third regions on both sides of the first section.

Abstract: A method for forming a semiconductor structure includes forming a dielectric layer with an opening on a substrate; forming a material film in the opening; forming a blocking film on the material film; and removing the blocking film at the bottom of the opening to expose the material film. The remaining blocking film forms an initial blocking layer. The method further includes forming a conductive-material film in the opening; performing an annealing process to form a contact layer at the bottom of the opening by making the substrate, the material film, and the conductive-material film react with each other; and planarizing the conductive-material film, the initial blocking layer, and the material film to expose the dielectric layer. The remaining initial blocking layer forms a blocking layer in the opening; and the remaining conductive-material film forms a plug in contact with the blocking layer and the contact layer.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.