Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a to-be-processed base structure, where the to-be-processed base structure includes a base layer and pattern structures protruding from the base layer, and a surface of the base structure has adsorption groups; performing plasma treatment on the surface of the base structure by using a reaction gas, where the reaction gas chemically reacts with the adsorption group to cause quantities of precursor adsorption nucleation points on the surface of the base structure to tend to be same; and after the plasma treatment, forming, by using an atomic layer deposition (ALD) process, a target layer conformally covering the surface of the base structure.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: Interconnect structures are provided. An interconnect structure includes a substrate; a first dielectric layer on the substrate and including an opening for a first interconnect layer extending to the substrate; a first metal layer having a first portion in the opening and a second portion in contact with the first portion and on a portion of the first dielectric layer adjacent to the opening; a second dielectric layer on the first dielectric layer and on the first metal layer, the second dielectric layer including a trench for a second interconnect layer, the trench exposing the second portion of the first metal layer; and a second metal layer in the trench, wherein the second portion of the first metal layer forms a lower portion of the second interconnect layer.

Abstract: A silicon-controlled-rectifier electrostatic protection structure and a fabrication method are provided. The structure includes: a substrate of P-type; a first N-type well, a second N-type well, and a third N-type well in the substrate; a first P-type doped region in the first N-type well; first N-type doped regions at sides of the first N-type well along a first direction; first gate structures on a portion of the first N-type doped regions and on a portion of the first P-type doped region; second gate structure groups at sides of the first N-type well along a second direction; second N-type doped regions in the substrate at sides of each second gate structure along the first direction; second P-type doped regions in the second N-type doped regions between adjacent second gate structure groups; and a third P-type doped region and a cathode N-type doped region in the substrate.

Abstract: A method for forming a semiconductor structure includes forming a dielectric layer on a substrate, including a first region and a second region; forming a first gate opening and a second gate opening in dielectric layer of the first region and the second region, respectively; forming initial work function layers on bottom and sidewall surfaces of the first gate opening and the second gate opening; and performing at least one cycle of a combined etching process to etch the initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the initial work function layers. Each cycle of the combined etching process includes performing an oxide etching process to etch the initial work function layers; and then performing a main etching process on the initial work function layers to remove an exposed initial work function layer.

Abstract: A semiconductor device includes: a substrate; a fin structure and a gate structure formed on the substrate; and a source/drain trench formed in the fin structure on each side of the gate structure. The source/drain trench includes a bottom region and a top region located above the bottom region. Along an extension direction of the fin structure, a dimension of the top region is larger than a dimension of the bottom region. Along the extension direction of the fin structure, a shortest distance from a sidewall surface of the top region of the source/drain trench to a sidewall surface of the gate structure is smaller than a shortest distance from a sidewall surface of the bottom region of the source/drain trench to the sidewall surface of the gate structure. The semiconductor device further includes a source/drain doped layer formed in the source/drain trench.

Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.

Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening.

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a substrate, where the substrate includes a shielding region having a first area; a first shielding layer on the substrate, where a first shielding structure is in the first shielding layer of the shielding region, and the first shielding structure has a first density; a second shielding layer on the first shielding layer, where a second shielding structure is in the second shielding layer of the shielding region, and the second shielding structure has a second density which is less than the first density; and an electrical interconnection structure, electrically interconnecting the first shielding structure with the second shielding structure and enabling the first shielding structure grounded.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate; forming at least one sacrificial layer and at least one liner layer, that are alternately stacked over each other, on the substrate; etching the at least one liner layer and the at least one sacrificial layer until the substrate is exposed, to form a plurality of fins, discretely arranged on the substrate; and etching a portion of a thickness of the substrate, such that a width of the etched portion of the substrate at a bottom of the at least one sacrificial layer is less than a width of the at least one liner layer of the plurality of fins.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least one first region, at least one second region and at least one third region; forming at least one first fin on the at least one first region, at least one second fin on the at least one second region and at least one third fin on the at least one third region; forming a first opening in the first fin; forming a second opening in the second fin; forming a first epitaxial layer in the first opening and the second opening; forming a third opening in the at least one third fin; removing at least a portion of the first epitaxial layer in the at least one second fin to form a fourth opening; and forming a second epitaxial layer in the third opening and the fourth opening.

Abstract: Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming an isolation structure on the first region and the second region of the substrate; forming a gate structure across the plurality of fins and on the isolation structure at the first region; etching the isolation structure and the substrate at the second region to form a first opening; filling the first opening with a conductive material layer; and etching the gate structure till exposing the isolation structure to form a second opening in the gate structure and removing a portion of the conductive material layer in the first opening to form a power rail.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region, a gate structure on the first region and a dummy gate structure on the second region, and an isolation structure in the semiconductor under the dummy gate structure. The method also includes forming source/drain openings in the semiconductor substrate at two sides of the gate structure. A sidewall surface of the source/drain opening contains an apex angle extending into the semiconductor substrate under the gate structure; and the source/drain opening exposes a sidewall surface of the isolation structure. Further; the method includes forming an initial bulk layer in the source/drain opening; performing a reshaping process to the initial bulk layer to form a bulk layer having an a substantially flat reshaped surface; and forming a protective layer on the bulk layer.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate, sequentially forming at least two sacrificial layers on the substrate, and forming a liner layer between any adjacent sacrificial layers of the at least two sacrificial layers. The method also includes forming a hard mask layer on a top layer of the at least two sacrificial layers, and sequentially etching the hard mask layer, the at least two sacrificial layers, the liner layer, and a portion of the substrate, thereby forming a plurality of fins that are discretely arranged on a remaining portion of the substrate. The method also includes forming a dummy gate structure across the plurality of fins on the remaining portion of the substrate, and removing a portion of the at least two sacrificial layers under the dummy gate structure, thereby forming tunnels.

Abstract: A magnetic random access memory cell and a method for forming a magnetic random access memory are provided. The memory cell includes a substrate including a plurality of active regions and a plurality of isolation regions each between adjacent active regions. The memory cell also includes a gate structure over each active region, and a word line structure over each isolation region. In addition, the memory cell includes a source region and a drain region in the substrate on both sides of the gate structure, and a dielectric structure over the substrate. The gate structure and the word line structure are located in the dielectric structure. Further, the memory cell includes a source line structure located in the dielectric structure and electrically connected to the source region over each active region. The word line structure, the gate structure, and the source line structure are parallel to each other.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first well region and a second well region in the semiconductor substrate; and forming a first gate structure on a surface of the second well region and a portion of a surface of the first well region and a second gate structure on a portion of the first well region. A first opening is formed between the first gate structure and the second gate structure. The method also include forming a sidewall spacer layer covering sidewall and bottom surfaces of the first opening in the first opening; forming a dielectric layer on the semiconductor substrate to cover the first gate structure, the second gate structure and the sidewall spacer layer; and forming a floating plug in the dielectric layer and on the sidewall spacer layer.

Abstract: A semiconductor device and its fabrication method are provided. The method includes providing a layer to be etched; forming a first mask layer on the layer to be etched; forming a first trench and a second trench in the first mask layer; forming a blocking layer over the first mask layer, where a portion of the blocking layer is formed in a first portion of the first trench and a first portion of the second trench; forming a first dividing layer in a first blocking opening to divide the first trench along a first direction; when forming the first dividing layer, forming second dividing layers on two sidewalls of a second blocking opening and arranged along the first direction, where the second dividing layers divide the second trench along the first direction; and after forming the first dividing layer and the second dividing layers, removing the blocking layer.

Abstract: A fingerprint sensor includes: a base substrate including a plurality of pixel regions; a sensing dielectric structure formed on the base substrate in the pixel regions; and a sensing connection structure formed in the sensing dielectric structure. The sensing dielectric structure exposes the sensing connection structure and the sensing connection structure is connected to the base substrate. The fingerprint sensor further includes a plurality of electrode plates formed on surfaces of the sensing dielectric structure and the sensing connection structure. A plurality of protrusions are formed on surfaces of the electrode plates. The fingerprint sensor further includes an insulation medium structure formed on the plurality of electrode plates.